Zero-Order Hold in control ystems

When you have digital control with feedback we take account of the ZOH in t=
he DAC. This is in all the textbooks and shows a pulse as the impulse respo=
nse and you get the sinc for the magnitude of it and a linear phase charact=
eristic. You then need to sample about 10 times the max freq of interest so=
 as not to get too much phase lag from this.

However, many systems nowadays have H bridges and no ZOH as such. Of course=
 there will always be a one-step delay to get round a loop so that too has =
a phase-lag. Are we to assume then that the ZOH is no longer a problem but =
we use a pure one step delay instead ie

z^-1 =3D exp(-sT)

where T is the sample interval in sec.

On Monday, February 13, 2017 at 9:10:54 AM UTC+13, gyans...@gmail.com wrote=
:
> When you have digital control with feedback we take account of the ZOH in=
 the DAC. This is in all the textbooks and shows a pulse as the impulse res=
ponse and you get the sinc for the magnitude of it and a linear phase chara=
cteristic. You then need to sample about 10 times the max freq of interest =
so as not to get too much phase lag from this.
>=20
> However, many systems nowadays have H bridges and no ZOH as such. Of cour=
se there will always be a one-step delay to get round a loop so that too ha=
s a phase-lag. Are we to assume then that the ZOH is no longer a problem bu=
t we use a pure one step delay instead ie
>=20
> z^-1 =3D exp(-sT)
>=20
> where T is the sample interval in sec.

Been giving it further thought and think we need the impulse response of an=
 H bridge which is also a pulse is it not so same result as ZOH

On Sun, 12 Feb 2017 12:10:52 -0800, gyansorova wrote:

> When you have digital control with feedback we take account of the ZOH
> in the DAC. This is in all the textbooks and shows a pulse as the
> impulse response and you get the sinc for the magnitude of it and a
> linear phase characteristic. You then need to sample about 10 times the
> max freq of interest so as not to get too much phase lag from this.
> 
> However, many systems nowadays have H bridges and no ZOH as such. Of
> course there will always be a one-step delay to get round a loop so that
> too has a phase-lag. Are we to assume then that the ZOH is no longer a
> problem but we use a pure one step delay instead ie
> 
> z^-1 = exp(-sT)
> 
> where T is the sample interval in sec.

It's more complicateder than that, and it's not even an "it", it's a 
"them".

If your PWM is front-loaded (i.e., if you always turn on at time t = nT_s, 
and vary the turn-off time) then the delay isn't constant.  Most PWMs 
center the "on" time around one periodically repeating event (by making 
the counter count up, then down, then up, etc.)  But the pulse width 
varies, so at very low duty cycles the thing acts more like an impulse, 
while at 50% duty cycle it's a square wave.

Also, depending on the PWM generator, there may be an extra clock (or 
half a clock) of delay, for systems that have hardware support for 
insuring that all of the PWM channels change their duty cycle 
simultaneously.

Fortunately, if you're using PWM then you're probably driving a motor, 
and it probably has enough inductance that the PWM at least is clocking 
at a lot higher than 10x your achievable bandwidth.  In that case, the 
response is dominated by things other than the output, and you don't have 
to worry as much.

I gave up on worrying about this sort of thing a long time ago, shortly 
after I noticed that I never, ever, get enough information from the 
mechanical designers to accurately model the loop.  I just work it out 
sorta-kinda in theory, and then make damned sure I take some Really Good 
measurements of the behavior of as many of the prototypes as I can lay my 
hands on. 

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

On Monday, February 13, 2017 at 2:12:41 PM UTC+13, Tim Wescott wrote:
> On Sun, 12 Feb 2017 12:10:52 -0800, gyansorova wrote:
> 
> > When you have digital control with feedback we take account of the ZOH
> > in the DAC. This is in all the textbooks and shows a pulse as the
> > impulse response and you get the sinc for the magnitude of it and a
> > linear phase characteristic. You then need to sample about 10 times the
> > max freq of interest so as not to get too much phase lag from this.
> > 
> > However, many systems nowadays have H bridges and no ZOH as such. Of
> > course there will always be a one-step delay to get round a loop so that
> > too has a phase-lag. Are we to assume then that the ZOH is no longer a
> > problem but we use a pure one step delay instead ie
> > 
> > z^-1 = exp(-sT)
> > 
> > where T is the sample interval in sec.
> 
> It's more complicateder than that, and it's not even an "it", it's a 
> "them".
> 
> If your PWM is front-loaded (i.e., if you always turn on at time t = nT_s, 
> and vary the turn-off time) then the delay isn't constant.  Most PWMs 
> center the "on" time around one periodically repeating event (by making 
> the counter count up, then down, then up, etc.)  But the pulse width 
> varies, so at very low duty cycles the thing acts more like an impulse, 
> while at 50% duty cycle it's a square wave.
> 
> Also, depending on the PWM generator, there may be an extra clock (or 
> half a clock) of delay, for systems that have hardware support for 
> insuring that all of the PWM channels change their duty cycle 
> simultaneously.
> 
> Fortunately, if you're using PWM then you're probably driving a motor, 
> and it probably has enough inductance that the PWM at least is clocking 
> at a lot higher than 10x your achievable bandwidth.  In that case, the 
> response is dominated by things other than the output, and you don't have 
> to worry as much.
> 
> I gave up on worrying about this sort of thing a long time ago, shortly 
> after I noticed that I never, ever, get enough information from the 
> mechanical designers to accurately model the loop.  I just work it out 
> sorta-kinda in theory, and then make damned sure I take some Really Good 
> measurements of the behavior of as many of the prototypes as I can lay my 
> hands on. 
> 
> -- 
> Tim Wescott
> Control systems, embedded software and circuit design
> I'm looking for work!  See my website if you're interested
> http://www.wescottdesign.com

Yes I make it that it's a variable delay as you say which means the phase margin must also vary with time but not the gain margin! The old 10-1 rule solves all problems as you say, I was just curious though. all the text books have this zero order hold thing but I also figured out a long time ago this was for the 1970s or 80s when micros were slow. Nowadays you just sample fast and the problems go away. In old books it talks of selection of sampling time - as if you have the luxury of making it anything you like! I dotn't know if academics just copied from one book into another or what

On Sun, 12 Feb 2017 19:43:29 -0800, gyansorova wrote:

> On Monday, February 13, 2017 at 2:12:41 PM UTC+13, Tim Wescott wrote:
>> On Sun, 12 Feb 2017 12:10:52 -0800, gyansorova wrote:
>> 
>> > When you have digital control with feedback we take account of the
>> > ZOH in the DAC. This is in all the textbooks and shows a pulse as the
>> > impulse response and you get the sinc for the magnitude of it and a
>> > linear phase characteristic. You then need to sample about 10 times
>> > the max freq of interest so as not to get too much phase lag from
>> > this.
>> > 
>> > However, many systems nowadays have H bridges and no ZOH as such. Of
>> > course there will always be a one-step delay to get round a loop so
>> > that too has a phase-lag. Are we to assume then that the ZOH is no
>> > longer a problem but we use a pure one step delay instead ie
>> > 
>> > z^-1 = exp(-sT)
>> > 
>> > where T is the sample interval in sec.
>> 
>> It's more complicateder than that, and it's not even an "it", it's a
>> "them".
>> 
>> If your PWM is front-loaded (i.e., if you always turn on at time t =
>> nT_s,
>> and vary the turn-off time) then the delay isn't constant.  Most PWMs
>> center the "on" time around one periodically repeating event (by making
>> the counter count up, then down, then up, etc.)  But the pulse width
>> varies, so at very low duty cycles the thing acts more like an impulse,
>> while at 50% duty cycle it's a square wave.
>> 
>> Also, depending on the PWM generator, there may be an extra clock (or
>> half a clock) of delay, for systems that have hardware support for
>> insuring that all of the PWM channels change their duty cycle
>> simultaneously.
>> 
>> Fortunately, if you're using PWM then you're probably driving a motor,
>> and it probably has enough inductance that the PWM at least is clocking
>> at a lot higher than 10x your achievable bandwidth.  In that case, the
>> response is dominated by things other than the output, and you don't
>> have to worry as much.
>> 
>> I gave up on worrying about this sort of thing a long time ago, shortly
>> after I noticed that I never, ever, get enough information from the
>> mechanical designers to accurately model the loop.  I just work it out
>> sorta-kinda in theory, and then make damned sure I take some Really
>> Good measurements of the behavior of as many of the prototypes as I can
>> lay my hands on.
>> 
>> --
>> Tim Wescott Control systems, embedded software and circuit design I'm
>> looking for work!  See my website if you're interested
>> http://www.wescottdesign.com
> 
> Yes I make it that it's a variable delay as you say which means the
> phase margin must also vary with time but not the gain margin! The old
> 10-1 rule solves all problems as you say, I was just curious though. all
> the text books have this zero order hold thing but I also figured out a
> long time ago this was for the 1970s or 80s when micros were slow.
> Nowadays you just sample fast and the problems go away. In old books it
> talks of selection of sampling time - as if you have the luxury of
> making it anything you like! I dotn't know if academics just copied from
> one book into another or what

I have worked on systems where the sample rate isn't handed to you on a 
platter, and you have to do some tradeoffs between the expense of faster 
sampling vs. the performance loss of slow sampling.

But then, I've worked on systems where the sampling rate is determined by 
one sensor or another, or by some comm link between bits.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!

On Sunday, February 12, 2017 at 3:10:54 PM UTC-5, gyans...@gmail.com wrote:
> When you have digital control with feedback we take account of the ZOH in the DAC. This is in all the textbooks and shows a pulse as the impulse response and you get the sinc for the magnitude of it and a linear phase characteristic. You then need to sample about 10 times the max freq of interest so as not to get too much phase lag from this.
> 
> However, many systems nowadays have H bridges and no ZOH as such. Of course there will always be a one-step delay to get round a loop so that too has a phase-lag. Are we to assume then that the ZOH is no longer a problem but we use a pure one step delay instead ie
> 
> z^-1 = exp(-sT)
> 
> where T is the sample interval in sec.

what'sa "H bridge"?

r b-j

On Monday, February 13, 2017 at 2:27:11 PM UTC-5, robert bristow-johnson wrote:
> On Sunday, February 12, 2017 at 3:10:54 PM UTC-5, gyans...@gmail.com wrote:
> > When you have digital control with feedback we take account of the ZOH in the DAC. This is in all the textbooks and shows a pulse as the impulse response and you get the sinc for the magnitude of it and a linear phase characteristic. You then need to sample about 10 times the max freq of interest so as not to get too much phase lag from this.
> > 
> > However, many systems nowadays have H bridges and no ZOH as such. Of course there will always be a one-step delay to get round a loop so that too has a phase-lag. Are we to assume then that the ZOH is no longer a problem but we use a pure one step delay instead ie
> > 
> > z^-1 = exp(-sT)
> > 
> > where T is the sample interval in sec.
> 
> what'sa "H bridge"?
> 
> r b-j

okay, now i know what an H bridge is.  so is this question about replacing a DAC with PWM?  is that it?

r b-j

On Tuesday, February 14, 2017 at 8:29:43 AM UTC+13, robert bristow-johnson wrote:
> On Monday, February 13, 2017 at 2:27:11 PM UTC-5, robert bristow-johnson wrote:
> > On Sunday, February 12, 2017 at 3:10:54 PM UTC-5, gyans...@gmail.com wrote:
> > > When you have digital control with feedback we take account of the ZOH in the DAC. This is in all the textbooks and shows a pulse as the impulse response and you get the sinc for the magnitude of it and a linear phase characteristic. You then need to sample about 10 times the max freq of interest so as not to get too much phase lag from this.
> > > 
> > > However, many systems nowadays have H bridges and no ZOH as such. Of course there will always be a one-step delay to get round a loop so that too has a phase-lag. Are we to assume then that the ZOH is no longer a problem but we use a pure one step delay instead ie
> > > 
> > > z^-1 = exp(-sT)
> > > 
> > > where T is the sample interval in sec.
> > 
> > what'sa "H bridge"?
> > 
> > r b-j
> 
> okay, now i know what an H bridge is.  so is this question about replacing a DAC with PWM?  is that it?
> 
> r b-j

Yes it is. What happens to the zero order hold equations. We think the phase changes with amplitude and is linear for an H bridge

On Mon, 13 Feb 2017 11:29:40 -0800, robert bristow-johnson wrote:

> On Monday, February 13, 2017 at 2:27:11 PM UTC-5, robert bristow-johnson
> wrote:
>> On Sunday, February 12, 2017 at 3:10:54 PM UTC-5, gyans...@gmail.com
>> wrote:
>> > When you have digital control with feedback we take account of the
>> > ZOH in the DAC. This is in all the textbooks and shows a pulse as the
>> > impulse response and you get the sinc for the magnitude of it and a
>> > linear phase characteristic. You then need to sample about 10 times
>> > the max freq of interest so as not to get too much phase lag from
>> > this.
>> > 
>> > However, many systems nowadays have H bridges and no ZOH as such. Of
>> > course there will always be a one-step delay to get round a loop so
>> > that too has a phase-lag. Are we to assume then that the ZOH is no
>> > longer a problem but we use a pure one step delay instead ie
>> > 
>> > z^-1 = exp(-sT)
>> > 
>> > where T is the sample interval in sec.
>> 
>> what'sa "H bridge"?
>> 
>> r b-j
> 
> okay, now i know what an H bridge is.  so is this question about
> replacing a DAC with PWM?  is that it?
> 
> r b-j

More like replacing a DAC + power amp with an H-bridge, but yes.

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

On Monday, February 13, 2017 at 7:41:57 PM UTC-5, gyans...@gmail.com wrote:
> On Tuesday, February 14, 2017 at 8:29:43 AM UTC+13, robert bristow-johnson wrote:
> > On Monday, February 13, 2017 at 2:27:11 PM UTC-5, robert bristow-johnson wrote:
> > > On Sunday, February 12, 2017 at 3:10:54 PM UTC-5, gyans...@gmail.com wrote:
> > > > When you have digital control with feedback we take account of the ZOH in the DAC. This is in all the textbooks and shows a pulse as the impulse response and you get the sinc for the magnitude of it and a linear phase characteristic. You then need to sample about 10 times the max freq of interest so as not to get too much phase lag from this.
> > > > 
> > > > However, many systems nowadays have H bridges and no ZOH as such. Of course there will always be a one-step delay to get round a loop so that too has a phase-lag. Are we to assume then that the ZOH is no longer a problem but we use a pure one step delay instead ie
> > > > 
> > > > z^-1 = exp(-sT)
> > > > 
> > > > where T is the sample interval in sec.
> > > 
> > > what'sa "H bridge"?
> > > 
> > 
> > okay, now i know what an H bridge is.  so is this question about replacing a DAC with PWM?  is that it?
> > 
> 
> Yes it is. What happens to the zero order hold equations. We think the phase changes with amplitude and is linear for an H bridge

okay, so the question is how is a PWM output modeled rather than PAM (pulse amplitude modulation).  we know that PAM output with a regular DAC makes use of a ZOH.  even for sigma delta, but the upsampled sample rate is so high that the effect of ZOH is negligible for the baseband.  so what is the sample rate for the PWM and what is the baseband for the net control signal?

r b-j