Precise and repeatable delay generation

Started by September 14, 2017
Hi all,

I am faced with the following problem. I need to generate 1MHz square wave where the
phase delay has to be controlled precisely and repeatedly. The duty cycle of this
signal can be anywhere between 40%-60%. The delay should be able to be incremented
in approx. 10ps steps and the resulting 1MHz square wave jitter needs to be around
100fs or better. I was thinking about using DDS implemented in FPGA that would be
driving 400MS/s external 14 bit DAC. 400MHz low jitter TCXO would provide the clock
to this DAC. DDS would be driving DAC to generate 32MHz sine wave and that would be
fed to the input of low jitter divider like AD9515 to divide it down to 1MHz and
reduce the jitter. DDS could finely adjust the sine wave phase thus controlling 1MHz
square wave phase.

The main problem is that the DAC of above spec is quite expensive. Any thought about
using different system architecture/approach to satisfy above requirements and
reduce the cost?

Kind regards,
Adam
On Thu, 14 Sep 2017 07:10:06 -0700, a.turowski wrote:

> Hi all, > > I am faced with the following problem. I need to generate 1MHz square > wave where the phase delay has to be controlled precisely and > repeatedly. The duty cycle of this signal can be anywhere between > 40%-60%. The delay should be able to be incremented in approx. 10ps > steps and the resulting 1MHz square wave jitter needs to be around 100fs > or better. I was thinking about using DDS implemented in FPGA that would > be driving 400MS/s external 14 bit DAC. 400MHz low jitter TCXO would > provide the clock to this DAC. DDS would be driving DAC to generate > 32MHz sine wave and that would be fed to the input of low jitter divider > like AD9515 to divide it down to 1MHz and reduce the jitter. DDS could > finely adjust the sine wave phase thus controlling 1MHz square wave > phase. > > The main problem is that the DAC of above spec is quite expensive. Any > thought about using different system architecture/approach to satisfy > above requirements and reduce the cost? > > Kind regards, > Adam
You didn't define "repeatedly" - this might impact the possible architectures. Thinking outside the box: A completely different (but not necessarily cheaper) way of doing it could involve a high speed transceiver on one of the newer FPGA families. The maximum data rate is about twenty-something Gb/s, which would limit you to about 35ps steps, if using full bits. This doesn't meet your 10ps specification, but you do have the advantage of not needing a DAC, filter, comparator and AD9515. Some of the FPGA transceivers provide access to a phase interpolator on the transceiver output, giving the ability to control output edges to a fraction of a bit period. This could easily meet your 10ps step requirement. You'll still need the TXCO and a frequency synthesiser to provide the reference clock for the FPGA transceiver. BTW, you won't find a "400MHz low jitter TXCO" - you'll use a lower frequency one and something like a Silicon Labs Si5340 to synthesise 400MHz from that. For that matter, the Si5340 itself claims to have trimmable phase on each output. From the datasheet: "Each delay path is controlled by a register parameter call Nx_DELAY with a resolution of ~0.28 ps over a range of ~ ±9.14 ns." It needs a reset after changing the delay though. BTW, there are synths with lower jitter that the Si5340 (e.g. Si5380A, designed for JESD204B clocking) but the Si5340A is the lowest jitter one that I have actually used in a product. References: Xilinx UG576 https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale- gth-transceivers.pdf Silicon Labs Si5340 datasheet. https://www.silabs.com/products/timing/clocks/high-performance-clock- generators/device.si5340a Regards, Allan
On Thu, 14 Sep 2017 07:10:06 -0700, a.turowski wrote:

> Hi all, > > I am faced with the following problem. I need to generate 1MHz square > wave where the phase delay has to be controlled precisely and > repeatedly. The duty cycle of this signal can be anywhere between > 40%-60%. The delay should be able to be incremented in approx. 10ps > steps and the resulting 1MHz square wave jitter needs to be around 100fs > or better. I was thinking about using DDS implemented in FPGA that would > be driving 400MS/s external 14 bit DAC. 400MHz low jitter TCXO would > provide the clock to this DAC. DDS would be driving DAC to generate > 32MHz sine wave and that would be fed to the input of low jitter divider > like AD9515 to divide it down to 1MHz and reduce the jitter. DDS could > finely adjust the sine wave phase thus controlling 1MHz square wave > phase. > > The main problem is that the DAC of above spec is quite expensive. Any > thought about using different system architecture/approach to satisfy > above requirements and reduce the cost? > > Kind regards, > Adam
You might like to ask this question on news:sci.electronics.design The designer of the products on this page: http://www.highlandtechnology.com/categories/digital_delay_generators.shtml is a frequent poster in that newsgroup. Regards, Allan
a.turowski@ymail.com wrote on 9/14/2017 10:10 AM:
> Hi all, > > I am faced with the following problem. I need to generate 1MHz square wave where
the phase delay has to be controlled precisely and repeatedly. The duty cycle of this signal can be anywhere between 40%-60%. The delay should be able to be incremented in approx. 10ps steps and the resulting 1MHz square wave jitter needs to be around 100fs or better. I was thinking about using DDS implemented in FPGA that would be driving 400MS/s external 14 bit DAC.. 400MHz low jitter TCXO would provide the clock to this DAC. DDS would be driving DAC to generate 32MHz sine wave and that would be fed to the input of low jitter divider like AD9515 to divide it down to 1MHz and reduce the jitter. DDS could finely adjust the sine wave phase thus controlling 1MHz square wave phase.
> > The main problem is that the DAC of above spec is quite expensive. Any thought
about using different system architecture/approach to satisfy above requirements and reduce the cost? If you need a delay, stable and repeatable on the order of 10 ps with jitter of 100 fs, then I think you need to think simple rather than complex. An FPGA can have variable signal path delays dependent on temperature, so this might be a bit too complex. The adjustment can be done by using a differential input such as an ECL device. The incoming square wave would be on one input. The other input would be driven by a DAC. Taking advantage of the slope of the digital input you can adjust the DAC output to control the threshold and so the timing of the output. You may want to create a controlled slope by running the square wave through an RC circuit to shape the edges exactly to suit your needs. You will need to use a temperature insensitive cap such as NP0 and possibly also control the ambient temperature to get an adequately stable delay in the electronics. Do you have a way of measuring the delay so it can be controlled in a loop? If so, the above circuit could be used to produce stable delays easily without the fuss about temperature. Otherwise the circuit will need to be calibrated and temperature controlled. -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998
> I am faced with the following problem. I need to generate 1MHz square > wave where the phase delay has to be controlled precisely and > repeatedly. The duty cycle of this signal can be anywhere between > 40%-60%. The delay should be able to be incremented in approx. 10ps > steps and the resulting 1MHz square wave jitter needs to be around 100fs > or better. I was thinking about using DDS implemented in FPGA that would > be driving 400MS/s external 14 bit DAC.. 400MHz low jitter TCXO would > provide the clock to this DAC. DDS would be driving DAC to generate > 32MHz sine wave and that would be fed to the input of low jitter divider > like AD9515 to divide it down to 1MHz and reduce the jitter. DDS could > finely adjust the sine wave phase thus controlling 1MHz square wave > phase.
One specification you have not mentioned is to how much accuracy must this signal must have frequency of exactly 1 MHz. Also, whether you need build lots of these, or just a few. Since, my first thought would be do build this thing using connectorized components to avoid tricky PCB layouts, etc. The ENOB of a 14 bit DAC is not 14 bits and any digital noise could blow away your spec. I would avoid the DAC (somwhow). Your phase noise spec is -70 dBc (if I'm interpreting your numbers correctly). That, to me, says this is instrumentation grade, not mass-producable at low cost, but somebody tell me I'm wrong. On technique I have heard of is to use very high Q tank circuits to reduce the phase noise of an oscillator when that oscillator only need oscillate at one frequency, as is the case for you. I haven't done this in pracice, myself. Good luck - Steve
W dniu niedziela, 17 września 2017 00:38:46 UTC+1 użytkownik Steve Pope
napisał:
> > I am faced with the following problem. I need to generate 1MHz square > > wave where the phase delay has to be controlled precisely and > > repeatedly. The duty cycle of this signal can be anywhere between > > 40%-60%. The delay should be able to be incremented in approx. 10ps > > steps and the resulting 1MHz square wave jitter needs to be around 100fs > > or better. I was thinking about using DDS implemented in FPGA that would > > be driving 400MS/s external 14 bit DAC.. 400MHz low jitter TCXO would > > provide the clock to this DAC. DDS would be driving DAC to generate > > 32MHz sine wave and that would be fed to the input of low jitter divider > > like AD9515 to divide it down to 1MHz and reduce the jitter. DDS could > > finely adjust the sine wave phase thus controlling 1MHz square wave > > phase. > > One specification you have not mentioned is to how much accuracy must > this signal must have frequency of exactly 1 MHz. > > Also, whether you need build lots of these, or just a few. > Since, my first thought would be do build this thing using connectorized > components to avoid tricky PCB layouts, etc. The ENOB of a 14 bit > DAC is not 14 bits and any digital noise could blow away your spec. > I would avoid the DAC (somwhow). > > Your phase noise spec is -70 dBc (if I'm interpreting your numbers > correctly). That, to me, says this is instrumentation grade, not > mass-producable at low cost, but somebody tell me I'm wrong. > > On technique I have heard of is to use very high Q tank circuits > to reduce the phase noise of an oscillator when that oscillator > only need oscillate at one frequency, as is the case for you. > I haven't done this in pracice, myself. > > Good luck - > > Steve
Hi all, Thanks for all the replies. Let me give you some more background so it will help you to understand the problem better. The purpose of the system is to estimate precisely the time of arrival of each pulse in the train of 1000 of UWB pulses. Each pulse is transmitted every 1us, so the whole pulse train is 1ms long. The pulses are being generated by simple single transistor 6.5GHz generator where its power supply is applied for approx 3ns every 1us (1MHz repetition rate). The power supply triggering is controlled by low jitter TCXO. As tested with the oscilloscope each pulse is approx. 1.5ns long part of 6.5GHz sine wave. It is simply couple of cycles of sine wave and the leading and trailing cycles are not full amplitude. The purpose of the receiver is to detect the pulses and estimate when exactly they arrive with regards to receiver low jitter clock. This clock is independent from the transmitter's clock. The idea is to first roughly estimate received pulses timing with simple power detector being sampled by FPGA at say 1Gsps rate. This would be done at some of the initial pulses in the train and provide +/-1ns estimate when to expect the next pulses. Having this initial estimate we could generate our local UWB pulse and use a mixer to cross-correlate it with received UWB pulses. Integrated output of the mixer would provide cross-correlation function value for given time offset between local and received pulse. Being able to precisely control the time delay to trigger local UWB pulse allows for search for the maximum of cross-correlation function giving an information when the pulse has been received. As I stated, it is just an idea how to solve the receiving problem. I am open to other suggestions regarding the whole receiver architecture. Couple of thousands of these systems will need to be built, so cost is important. Kind regards, Adam
W dniu poniedziałek, 18 września 2017 10:15:27 UTC+1 użytkownik
a.tur...@ymail.com napisał:
> W dniu niedziela, 17 września 2017 00:38:46 UTC+1 użytkownik Steve Pope
napisał:
> > > I am faced with the following problem. I need to generate 1MHz square > > > wave where the phase delay has to be controlled precisely and > > > repeatedly. The duty cycle of this signal can be anywhere between > > > 40%-60%. The delay should be able to be incremented in approx. 10ps > > > steps and the resulting 1MHz square wave jitter needs to be around 100fs > > > or better. I was thinking about using DDS implemented in FPGA that would > > > be driving 400MS/s external 14 bit DAC.. 400MHz low jitter TCXO would > > > provide the clock to this DAC. DDS would be driving DAC to generate > > > 32MHz sine wave and that would be fed to the input of low jitter divider > > > like AD9515 to divide it down to 1MHz and reduce the jitter. DDS could > > > finely adjust the sine wave phase thus controlling 1MHz square wave > > > phase. > > > > One specification you have not mentioned is to how much accuracy must > > this signal must have frequency of exactly 1 MHz. > > > > Also, whether you need build lots of these, or just a few. > > Since, my first thought would be do build this thing using connectorized > > components to avoid tricky PCB layouts, etc. The ENOB of a 14 bit > > DAC is not 14 bits and any digital noise could blow away your spec. > > I would avoid the DAC (somwhow). > > > > Your phase noise spec is -70 dBc (if I'm interpreting your numbers > > correctly). That, to me, says this is instrumentation grade, not > > mass-producable at low cost, but somebody tell me I'm wrong. > > > > On technique I have heard of is to use very high Q tank circuits > > to reduce the phase noise of an oscillator when that oscillator > > only need oscillate at one frequency, as is the case for you. > > I haven't done this in pracice, myself. > > > > Good luck - > > > > Steve > > Hi all, > > Thanks for all the replies. Let me give you some more background so it will help
you to understand the problem better. The purpose of the system is to estimate precisely the time of arrival of each pulse in the train of 1000 of UWB pulses. Each pulse is transmitted every 1us, so the whole pulse train is 1ms long.
> > The pulses are being generated by simple single transistor 6.5GHz generator where
its power supply is applied for approx 3ns every 1us (1MHz repetition rate). The power supply triggering is controlled by low jitter TCXO. As tested with the oscilloscope each pulse is approx. 1.5ns long part of 6.5GHz sine wave. It is simply couple of cycles of sine wave and the leading and trailing cycles are not full amplitude.
> > The purpose of the receiver is to detect the pulses and estimate when exactly they
arrive with regards to receiver low jitter clock. This clock is independent from the transmitter's clock. The idea is to first roughly estimate received pulses timing with simple power detector being sampled by FPGA at say 1Gsps rate. This would be done at some of the initial pulses in the train and provide +/-1ns estimate when to expect the next pulses. Having this initial estimate we could generate our local UWB pulse and use a mixer to cross-correlate it with received UWB pulses. Integrated output of the mixer would provide cross-correlation function value for given time offset between local and received pulse. Being able to precisely control the time delay to trigger local UWB pulse allows for search for the maximum of cross-correlation function giving an information when the pulse has been received.
> > As I stated, it is just an idea how to solve the receiving problem. I am open to
other suggestions regarding the whole receiver architecture. Couple of thousands of these systems will need to be built, so cost is important.
> > Kind regards, > Adam
Forgotten to add that each train of pulses seen by the receiver can be sent by different transmitter. Also there is no telling when the transmitter will start transmitting. So from receiver point of view each train is individual - no information from the previous train measurement can be used.
On Monday, September 18, 2017 at 2:15:27 AM UTC-7, a.tur...@ymail.com wrote:

(snip)

> The purpose of the system is to estimate precisely the time > of arrival of each pulse in the train of 1000 of UWB pulses. > Each pulse is transmitted every 1us, so the whole pulse > train is 1ms long.
> The pulses are being generated by simple single transistor > 6.5GHz generator where its power supply is applied for approx > 3ns every 1us (1MHz repetition rate). The power supply > triggering is controlled by low jitter TCXO. As tested with > the oscilloscope each pulse is approx. 1.5ns long part of > 6.5GHz sine wave. It is simply couple of cycles of sine wave > and the leading and trailing cycles are not full amplitude.
Seems to me that you have to carefully define what you mean by the arrival time. As the leading cycles are not full amplitude, which cycle do you count? Is there a threshold above which a cycle must be to count as the leading edge? This problem reminds me, maybe just a little, about collision detection in coaxial ethernet. The detection circuit measures the voltage on the line, after some filtering. It will be above a specific value if two signals are being received (or of one is being received while one is transmitting). The timing is not so important, but it does come into some calculations on round-trip time and cable length.
a.turowski@ymail.com wrote on 9/18/2017 5:15 AM:
> W dniu niedziela, 17 września 2017 00:38:46 UTC+1 użytkownik Steve Pope
napisał:
>>> I am faced with the following problem. I need to generate 1MHz square >>> wave where the phase delay has to be controlled precisely and >>> repeatedly. The duty cycle of this signal can be anywhere between >>> 40%-60%. The delay should be able to be incremented in approx. 10ps >>> steps and the resulting 1MHz square wave jitter needs to be around 100fs >>> or better. I was thinking about using DDS implemented in FPGA that would >>> be driving 400MS/s external 14 bit DAC.. 400MHz low jitter TCXO would >>> provide the clock to this DAC. DDS would be driving DAC to generate >>> 32MHz sine wave and that would be fed to the input of low jitter divider >>> like AD9515 to divide it down to 1MHz and reduce the jitter. DDS could >>> finely adjust the sine wave phase thus controlling 1MHz square wave >>> phase. >> >> One specification you have not mentioned is to how much accuracy must >> this signal must have frequency of exactly 1 MHz. >> >> Also, whether you need build lots of these, or just a few. >> Since, my first thought would be do build this thing using connectorized >> components to avoid tricky PCB layouts, etc. The ENOB of a 14 bit >> DAC is not 14 bits and any digital noise could blow away your spec. >> I would avoid the DAC (somwhow). >> >> Your phase noise spec is -70 dBc (if I'm interpreting your numbers >> correctly). That, to me, says this is instrumentation grade, not >> mass-producable at low cost, but somebody tell me I'm wrong. >> >> On technique I have heard of is to use very high Q tank circuits >> to reduce the phase noise of an oscillator when that oscillator >> only need oscillate at one frequency, as is the case for you. >> I haven't done this in pracice, myself. >> >> Good luck - >> >> Steve > > Hi all, > > Thanks for all the replies. Let me give you some more background so it will help
you to understand the problem better. The purpose of the system is to estimate precisely the time of arrival of each pulse in the train of 1000 of UWB pulses. What are UWB pulses? -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998
W dniu wtorek, 19 września 2017 23:18:43 UTC+1 użytkownik
herrman...@gmail.com napisał:
> On Monday, September 18, 2017 at 2:15:27 AM UTC-7, a.tur...@ymail.com wrote: > > (snip) > > Seems to me that you have to carefully define what you mean > by the arrival time. As the leading cycles are not full > amplitude, which cycle do you count? Is there a threshold > above which a cycle must be to count as the leading edge?
In the context of the receiver architecture I've described above, I define arrival time to be when the measured cross correlation value is maximum. However other definitions are allowed as long as they give repeatable results.