CIC interpolation implementation

Started by Wilton Helm December 18, 2017
I sent this to Rick, but thought maybe a wider reading would be beneficial.  I'm
designing a CIC interpolating filter (N = 3, M = 1, R = 15 if it matters) and I came
to a realization I hadn't had before and haven't ever heard anyone else mention. 
That often means there's something badly wrong with it, but I don't see it.  Let's
start with the traditional implementation:
    Three (N) differentiators at the low sample rate
    A zero stuffing rate multiplier
    Three (N) integrators at the higher sample rate

Now consider that the input to the first integrator is the output of the last
differentiator for 1 out of N samples (at the higher rate) and 0 for the next N-1
samples.  Then consider that the internal state and output of an integrator does not
change when the input is 0.  Does this not mean that an integrator after a zero
stuffing rate multiplier does exactly the same thing as it would do if it was before
the rate multiplier?

Of course, the remaining integrators typically do NOT have zero inputs, so must
operate at the higher sample rate (even though the second one adds the same value
for N times).  Nor should they be preceded by a zero stuffer, but rather by a sample
replicator.  Of course, in a synchronous system, a sample replicator would be the
output of the first integrator, because it won't change for N cycles.  (True
statement whether the first integrator is at the low rate or the high rate, which is
one reason this appears to be sound).

So the refactored CIC interpolator becomes:
   N differentiators at the low rate
   an integrator at the low rate
   (No zero stuffer or anything special other than making sure the
    integrator output is available for the next N high rate clocks)
   N-1 integrators at the high rate

Am I missing something obvious here?  I think CIC interpolation just got a bit more
cost effective (computationally).  I can't discern any difference in the behavior,
other than the power consumption of the first integrator went down by about N and
there is no need for anything filling the role of a zero stuffer.  Even the bit
growth issues should not change.

Wilton
You are correct but you can go one step further. The last slow-rate integrator
cancels the previous slow-rate differentiator so you can eliminate both. You need a
zero-order-hold but that comes for free as you mentioned. 

The industrial realizations that I’m aware of mostly use this trick, but you
won’t find it in the literature for some reason. 

Bob
Zero-order-hold is a term I'm not familiar with, and apparently isn't as widely used
as some.  Am I correctly inferring that it is just holding the value of the last
slow rate stage for N fast rate clocks?

Interesting that it is widely used and yet not in the literature.  There are at
least a half dozen people who have written widely on DSP topics, including CIC, with
a practical emphasis on computational efficiency.  You'd think it would get picked
up somewhere.

Once I get it implemented and tested I'll do my part to try and spread the message.

Wilton
Wilton Helm  <wcjmhelm@gmail.com> wrote:

>Interesting that it is widely used and yet not in the literature. There >are at least a half dozen people who have written widely on DSP topics, >including CIC, with a practical emphasis on computational efficiency. >You'd think it would get picked up somewhere.
Perhaps because there's a difference between discussing an algorithm in the literature, where is is organized for conceptual clarity, and implementing the algorithm. S.
hi Bob,

Dana Massie kindly pointed me to this excellent article by Richard Lyons, which
includes the optimization described.

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1657825 

Reducing CIC Filter Complexity

Ricardo A. Losada and Richard Lyons 

cheers,
-Brian Clark
Thanks. 
A related topic is the so-called noble identities, which are not widely taught but
are very useful in multi-rate filter design. 

Bob
Wilton Helm <wcjmhelm@gmail.com> writes:

> Zero-order-hold is a term I'm not familiar with, and apparently isn't > as widely used as some. Am I correctly inferring that it is just > holding the value of the last slow rate stage for N fast rate clocks?
A zero-order hold is a continuous-time transfer function. The impulse response of a zero-order hold is 1, 0 <= t < T_s, where T_s is the sample period. It is (was?) often used to model the operation of a DAC which held each digital sample constant until the next digital sample. I don't remember seeing it applied to a multi-rate system. See https://en.wikipedia.org/wiki/Zero-order_hold. -- Randy Yates, DSP/Embedded Firmware Developer Digital Signal Labs http://www.digitalsignallabs.com
On Thursday, January 4, 2018 at 3:26:29 PM UTC-5, Randy Yates wrote:
> Wilton Helm <wcjmhelm@gmail.com> writes: > > > Zero-order-hold is a term I'm not familiar with, and apparently isn't > > as widely used as some. Am I correctly inferring that it is just > > holding the value of the last slow rate stage for N fast rate clocks?
it's holding it for any specified period of time. even 1 fast-rate clock.
> > A zero-order hold is a continuous-time transfer function. The impulse > response of a zero-order hold is 1, 0 <= t < T_s, where T_s is the > sample period.
remember our "T" problem and dimensional analysis discussion we've had in times of old here on comp.dsp. since the dimension of h(t) must be 1/time (if H(s) is dimensionless, which it is if the output and the input are the same dimension of "stuff"), i think the impulse response of a ZOH is 1/T_s when 0 <= t < T_s, despite what is popular in the textbooks. For the DC gain of a ZOH to be 1, the impulse response must have an area of 1 also.
> It is (was?) often used to model the operation of a DAC > which held each digital sample constant until the next digital sample.
well, if you're gonna model the sigma-delta at the high sample rate, the DAC and the analog feedback in the ADC, would still be modeled with a ZOH.