systolic implementation

Started by tradewind June 16, 2005
Hi,
Do you have examples (or simulation) of systolic implementation of the
QR-RLS algorithm in Adaptive Filter Theory (Haykin's book)? I found it
difficult to understand just by reading!
Thanks.

"tradewind" <vinhfq@gmail.com> wrote in message 
news:1118975335.175478.127320@g49g2000cwa.googlegroups.com...
> Hi, > Do you have examples (or simulation) of systolic implementation of the > QR-RLS algorithm in Adaptive Filter Theory (Haykin's book)? I found it > difficult to understand just by reading! > Thanks. >
I don't have the book and I'm not an expert on QR-RLS algo. Does it help to know that a systolic implementation is a multiprocessor approach? The idea is that interim results "pump" through a chain of processors that are each dedicated to one part of the process. It was a bandwagon the mid-1980's. I don't think I've heard much about it since. Note: in those days getting high throughput processing often seemed to be a matter of using more processors and brought with it all manner of communication and memory access issues. Some board manufacturers seem to have done a pretty good job of making multiprocessor boards with useful communication and memory access architectures. I worked on a project at Honeywell that provided back-end 8-processor TMS320C30 accelerator boards for the Intel iPSC2 "hypercube" (Multibus II). We sold an accelerated iPSC2 to the Navy. Otherwise we were too invisible in the market to make a commercial splash of it. And, I'm sure the market for specialized boards like this is limited (even with a more main-stream bus interface). Maybe Al would comment. Our next attempt was a 16-processor TMS320C40 with two communication mechanisms: a bus and the COM ports in a mesh. The original was on a 15"x15" board with daughterboards for the processors or board-edge I/O (up to 20 of them). The eventual idea was to use chip-on-board with the whole thing on a liquid cooled SEM E card (roughly 4"x5"). We won the Navy contract to build it but COTS took over right then and the project died (appropriately so). I still wonder to this day what the programming protocols would have been for it - in terms of which communication mechanism would be used for what (e.g. data vs. control / bus vs. COM port mesh). In those days of designing multiprocessor systems we liked to believe that Mercury got their idea for their RACE architecture from us. We also manufactured a couple of Warp machines for DARPA in the early 80's. That was another multiprocessor architecture. This was the end of my pursuits in processors that might have lent themselves to systolic approaches. After losing out to the Pentium in competition with our TMS320C80 boards at PDI, I ventured into doing image processing using quad Pentiums - multithreaded software, etc..... It might have worked out but the Intel server platforms necessary didn't seem to match a more traditionally "embedded" application space. But this was certainly parallel processing of the more typical variety and definitely not intended to be systolic anything. Of course, in *these* days it still comes up. Witness the multicore processors that are coming to market for PCs, etc. Any more, I'm not sure what a systolic approach really buys.... and maybe never did know for sure! There was a lot of DARPA hype in the 80's.... The devil is in the details. Fred