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Re: Undersampling of a clean carrier

Started by Paul Solomon September 14, 2005
"Paul Solomon" <psolomon@tpg.com.au> wrote in message 
news:431e07ae$1@dnews.tpgi.com.au...
> > "Thomas Magma" <somewhere@overtherainbow.com> wrote in message > news:dXiTe.402841$5V4.32336@pd7tw3no... >> >> "Paul Solomon" <psolomon@tpg.com.au> wrote in message >> news:4316590d@dnews.tpgi.com.au... >>> Hi, >>> >>> I have just been doing some test and I noticed a concerning problem that >>> I may be having with the undersampling design (for FM demod). >>> >>> I basically set up my board so that the adc input (which is clocked at >>> 80MHz) feeds directly into a DAC also clocked at 80MHz. >>> >>> If I put a 20MHz tone (clean sine wave CW) on the input (from a signal >>> generator) I get a clean 20MHz tone present on the output of the DAC >>> when >>> I look at it ona spectrum analyser. The output shows about 60dB Signal >>> to >>> the first intermod which is at 20.235 MHz.. >>> >>> If I put a 100MHz tone into the ADC input, I was expecting a similar >>> result as there is no other signals in the present, so this should >>> appear >>> as a clead 20MHz carrier on the DAC output. However on the output I do >>> get my 20MHz carrier, but the SNR reduced to 35dB to the first intermod >>> at 20.235MHz and there appears to be a lot of phase noise arond the >>> carrier. >>> >>> I have checked and double checked the input signals and they are very >>> clean showing about 80dB SNR (which is the max I can see on the spec an >>> anyway). >>> >>> The bitwidth of the ADC is 12 bits and the DAC is 14 bits. The ADC is >>> 2's >>> compliment and the DAC is unsigned. So to connect the ADC to the DAC I >>> have basically got. >>> >>> DAC[13] = ~ADC[11]; >>> DAC[12] = ADC[10]; >>> DAC[11] = ADC[9]; >>> DAC[10] = ADC[8]; >>> DAC[9] = ADC[7]; >>> DAC[8] = ADC[6]; >>> DAC[7] = ADC[5]; >>> DAC[6] = ADC[4]; >>> DAC[5] = ADC[3]; >>> DAC[4] = ADC[2]; >>> DAC[3] = ADC[1]; >>> DAC[2] = ADC[0]; >>> DAC[1] = 0; >>> DAC[0] = 0; >>> >>> the MSB is inverted to convert from signed to unsigned. >>> >>> Do these results sound like what you would expect to see or can anyone >>> see what I could be doing wrong here? I was not expecting an >>> undersampled >>> signal to have such poor SNR. >>> >>> Regards, >>> >>> Paul Solomon >>> >> >> Did you find where the problem was? I'm kind of curious as to where the >> source of your problems were. >> > > Hi, > > I still havnt gotten to the bottom of this one, however I have now gotten > to > the stage where I believe that the source of the probmen could be clock > jitter on the 2s60 dev board that I am using. As I have taken the design > down to just an adc and a clk and it works on my old 1s25 dev board fine > but > I get this probleme when run on the new 2s60 dev board. I am currently now > chasing the problem up with altera. > > I will let you know when the issue is resolved. > > Regards, > > Paul > >
Hi All, For those that are interested or were watching this thread I have finally gotten to the bottom of this problem. It turns out to have been hardware related which I was not expecting as I was using a brond new dev board. The problem was two fold. Firstly, the crystal oscillator that was onboard must be broken or very very cheap as it had terribly phase noise, like on a 1MHz span the CW looked like a christmas tree going out to about -50dBc at 500kHz out. So I replaced that and found that I still had an issue sidebands or intermods or something at ~200kHz out. After further investigation I discovered that these intermods were coming from the oscillator only when it was on the dev board and it turned out to be insufficient decoupling of the power supply, or it could have just been poor regulation as well.. Either way, by adding 1000uF to the VCC/GND ping of the crystal oscillator I was able to reduce these sidebands down from -55dBc to ~-80dBc which is more than sufficient for my application. Thanks for the help along the way. Regards, Paul Solomon
> Hi All, > > For those that are interested or were watching this thread I have finally > gotten to the bottom of this problem. It turns out to have been hardware > related which I was not expecting as I was using a brond new dev board. > The problem was two fold. Firstly, the crystal oscillator that was onboard > must be broken or very very cheap as it had terribly phase noise, like on > a 1MHz span the CW looked like a christmas tree going out to about -50dBc > at 500kHz out. So I replaced that and found that I still had an issue > sidebands or intermods or something at ~200kHz out. After further > investigation I discovered that these intermods were coming from the > oscillator only when it was on the dev board and it turned out to be > insufficient decoupling of the power supply, or it could have just been > poor regulation as well.. Either way, by adding 1000uF to the VCC/GND ping > of the crystal oscillator I was able to reduce these sidebands down > from -55dBc to ~-80dBc which is more than sufficient for my application. > > Thanks for the help along the way. > > Regards, > > Paul Solomon >
Hi Paul, Thanks for enlightening us on the solution to your problem. Often people will take their knowledge of discovery and clam up after they solve a problem. So kudos to you. Good luck with your undersampling project. I just completed one myself that did phase demodulation using the 450 th negative image. There are so many advantages to DSP demodulation that it's almost sad I have to shelf 90% of my analog career :( Thomas
On Wed, 14 Sep 2005 22:27:59 +1000, "Paul Solomon"
<psolomon@tpg.com.au> wrote:

>
(snipped)
>Hi All, > >For those that are interested or were watching this thread I have finally >gotten to the bottom of this problem. It turns out to have been hardware >related which I was not expecting as I was using a brond new dev board. The >problem was two fold. Firstly, the crystal oscillator that was onboard must >be broken or very very cheap as it had terribly phase noise, like on a 1MHz >span the CW looked like a christmas tree going out to about -50dBc at 500kHz >out. So I replaced that and found that I still had an issue sidebands or >intermods or something at ~200kHz out. After further investigation I >discovered that these intermods were coming from the oscillator only when it >was on the dev board and it turned out to be insufficient decoupling of the >power supply, or it could have just been poor regulation as well.. Either >way, by adding 1000uF to the VCC/GND ping of the crystal oscillator I was >able to reduce these sidebands down from -55dBc to ~-80dBc which is more >than sufficient for my application. > >Thanks for the help along the way. > >Regards, > >Paul Solomon
Hi Paul, Thanks for keeping us informed. It's practical, useful, real-world posts like yours that make this Newsgroup so useful to us all. Good work Paul! [-Rick-]