Hello I need to sample and demodulate an AM-signal that is between 30 kHz to 100 kHz. The signal has a bandwidth of about 10 kHz. What approach should I use? I�m thinking of using a 16 bit ADC with a maximum sampling frequency of 500 ksps. Maybe using an FPGA to control the ADC. The FPGA can also be used to do the signal processing. How high sampling frequency should I use?
Approach to demodulating AM-signals?
Started by ●March 3, 2006
Reply by ●March 3, 20062006-03-03
Mr M wrote:> Hello > > > > I need to sample and demodulate an AM-signal that is between 30 kHz to 100 > kHz. The signal has a bandwidth of about 10 kHz. > > > > What approach should I use? > > > > I�m thinking of using a 16 bit ADC with a maximum sampling frequency of 500 > ksps. Maybe using an FPGA to control the ADC. The FPGA can also be used to > do the signal processing. > > > > How high sampling frequency should I use? > >High enough so that your reception works. Nyquist in this case is 220kHz. You need to juggle the sophistication of your anti-aliasing filters vs. the speed requirements of your algorithm. All I can say for sure is that the smallest realistic sampling rate is around 300kHz. I would also be concerned about that 10kHz signal riding on a 30kHz carrier -- you're going to have some aliasing there, too, that will make a simple envelope detector output look pretty crude and rude. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/
Reply by ●March 3, 20062006-03-03
Mr M wrote:> Hello > > > > I need to sample and demodulate an AM-signal that is between 30 kHz to 100 > kHz. The signal has a bandwidth of about 10 kHz. > > > > What approach should I use? > > > > I�m thinking of using a 16 bit ADC with a maximum sampling frequency of 500 > ksps. Maybe using an FPGA to control the ADC. The FPGA can also be used to > do the signal processing. > > > > How high sampling frequency should I use?Is there any tuning ahead of the ADC? Are there signals that need to be rejected digitally? There's nothing in your description that rules out detecting with a simple rectifier, but nor is there an indication that that would be enough. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●March 3, 20062006-03-03
"Mr M" <blobb@bredband.net> wrote in message news:4408965c$0$15784$14726298@news.sunsite.dk...> Hello > > > > I need to sample and demodulate an AM-signal that is between 30 kHz to 100 > kHz. The signal has a bandwidth of about 10 kHz. > > > > What approach should I use? > > > > I'm thinking of using a 16 bit ADC with a maximum sampling frequency of500> ksps. Maybe using an FPGA to control the ADC. The FPGA can also be used to > do the signal processing. > > > > How high sampling frequency should I use? > >I would sample at 320 kHz and implement a digital down converter and a cordic function in the FPGA. Since you have a fixed 10 kHz bandwidth your ddc can decimate by 20 (with cic filter) to get down to a 16 kHz complex sample rate. Then the 10 kHz final filter with 20 taps will be easy to design and can be implemented serially running off the 320 kHz ADC clock. Having the 16 kHz final clock will be helpful too if you plan to output standard 8 ksps audio, for example. The cordic block is simple to implement and if you are using xilinx it is already in the coregen library, I believe. So, in all, you would need: 2 mpys for input mixer ( or you can implement with cordic too if you can handle the coarser resolution) 1 cic filter 2 mpy for serial fir filter 1 cordic (you need one stage per output bit so probably about 16*32 = 512 ffs or this can be serialized too) You could probably gin this up on a spartan evm board in a matter of days. -Clark
Reply by ●March 3, 20062006-03-03
Hello Tim,> > I would also be concerned about that 10kHz signal riding on a 30kHz > carrier -- you're going to have some aliasing there, too, that will make > a simple envelope detector output look pretty crude and rude. >How about WDF low and high pass filtering, then cut the sign bit and smooth? Provided Mr.M means that he doesn't have a priori knowledge of where the signal will show up this would have to be something like a 23-25kHz HP and a 110Khz LP. If noise permits. Or find the signal and then track it with a resonant equivalent which would give better SNR. Regards, Joerg http://www.analogconsultants.com
Reply by ●March 3, 20062006-03-03
Joerg wrote:> Hello Tim, > >> >> I would also be concerned about that 10kHz signal riding on a 30kHz >> carrier -- you're going to have some aliasing there, too, that will >> make a simple envelope detector output look pretty crude and rude. >> > > How about WDF low and high pass filtering, then cut the sign bit and > smooth? Provided Mr.M means that he doesn't have a priori knowledge of > where the signal will show up this would have to be something like a > 23-25kHz HP and a 110Khz LP. If noise permits. > > Or find the signal and then track it with a resonant equivalent which > would give better SNR. > > Regards, Joerg > > http://www.analogconsultants.comWDF? Getting the absolute value and smoothing should be better -- you'll still have some aliasing products getting into the baseband (I think), but it'll be better. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/
Reply by ●March 3, 20062006-03-03
"Anonymous" <someone@microsoft.com> wrote in news:Lh1Of.51484$no3.37783@tornado.southeast.rr.com:> > "Mr M" <blobb@bredband.net> wrote in message > news:4408965c$0$15784$14726298@news.sunsite.dk... >> Hello >> >> >> >> I need to sample and demodulate an AM-signal that is between 30 kHz >> to 100 kHz. The signal has a bandwidth of about 10 kHz. >> >> >> >> What approach should I use? >> >> >> >> I'm thinking of using a 16 bit ADC with a maximum sampling frequency >> of > 500 >> ksps. Maybe using an FPGA to control the ADC. The FPGA can also be >> used to do the signal processing. >> >> >> >> How high sampling frequency should I use? >> >> > > I would sample at 320 kHz and implement a digital down converter and a > cordic function in the FPGA. Since you have a fixed 10 kHz bandwidth > your ddc can decimate by 20 (with cic filter) to get down to a 16 kHz > complex sample rate. Then the 10 kHz final filter with 20 taps will be > easy to design and can be implemented serially running off the 320 kHz > ADC clock. Having the 16 kHz final clock will be helpful too if you > plan to output standard 8 ksps audio, for example. > > The cordic block is simple to implement and if you are using xilinx it > is already in the coregen library, I believe. > > So, in all, you would need: > > 2 mpys for input mixer ( or you can implement with cordic too if you > can handle the coarser resolution) > 1 cic filter > 2 mpy for serial fir filter > 1 cordic (you need one stage per output bit so probably about 16*32 = > 512 ffs or this can be serialized too) > > You could probably gin this up on a spartan evm board in a matter of > days. > > -Clark > > >You could do this on an FPGA or you could use a programmable DSP. A SHARC could interface the ADC gluelessly and there are enough MIPs -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
Reply by ●March 3, 20062006-03-03
Hello Tim,> > WDF? >Well, yes, I thought that he'd like to get rid of switcher noises and stuff below 30kHz and talk radio in the AM band. Personally I'd use LC though.> Getting the absolute value and smoothing should be better -- you'll > still have some aliasing products getting into the baseband (I think), > but it'll be better. >If you use a tracking filter there shouldn't be much getting into baseband. Doesn't have to be WDF, as long as it is nice and steep and most of all stable against the occasional thunderstrom crackle (that's where WDFs are pretty good). Regards, Joerg http://www.analogconsultants.com
Reply by ●March 3, 20062006-03-03
Hello Al,> > You could do this on an FPGA or you could use a programmable DSP. A SHARC > could interface the ADC gluelessly and there are enough MIPs >No pun intended but that's going to be expensive and power hungry. My first thought would be a nice mixer from the analog world. But Mr.M would have to tell us whether he knows where in the given range the AM signal will show up. Regards, Joerg http://www.analogconsultants.com
Reply by ●March 4, 20062006-03-04
"Mr M" <blobb@bredband.net> wrote in message news:4408965c$0$15784$14726298@news.sunsite.dk...> Hello > > > > I need to sample and demodulate an AM-signal that is between 30 kHz to 100 > kHz. The signal has a bandwidth of about 10 kHz. > > > > What approach should I use? > > > > I'm thinking of using a 16 bit ADC with a maximum sampling frequency of500> ksps. Maybe using an FPGA to control the ADC. The FPGA can also be used to > do the signal processing. > > > > How high sampling frequency should I use? > >Why not just use a diode and a capacitor - !! Tam
