hello,erevyone.Recently I have been designing a blind channel equalizer
based on the Constant Modulus Alogrithm.But I have a question that I
can't think over.The question is as follows:
The alogrithm I use is below:
the transmitted signal is modulated by the QPSK.The samples out of AD
must be real,I guess.
If I was right ,then how to deal with the conjucate in the DSP
program.If I am wrong,please tell me why. Many thanks.
Reply by Phil●April 18, 20062006-04-18
How come you have real samples if the constellation is QPSK. This
modulation format implies complex samples, or a real I and a real Q
pair per sample.
Reply by ●April 18, 20062006-04-18
tirst of all,thank you for you reply.Now I know,when equalizing the
qpsk signal, I have to sample the I and Q channel respctivly,where the
I and Q stand for the real part and imaginant part.However I met
another question,that is the simulating property is not
stable.Sometimes,it's very good,then sometimes it becomes very bad.The
property relates to the channel .But it's the blind equalizer.How can
I guarntee the implemention on dsp is good?
Adjusting the step size mu ,or increase the SNR,and the length of the
equalizer? I find when the step size becomes smaller,the result does
not become better.
Any suggestion appreciate.
Reply by Phil●April 19, 20062006-04-19
If I understand correctly, you are observing the equaliser lock and
then loose lock on your signal. I assume that you are basing this on
observation of e(k).
Actually, to avoid inacurate assumptions and wasted time, could you
better explain the channel dynamics and the algorithms/circuits that
precede and follow the equaliser? Also clarify what you are observing
when you state that it is not stable.
It is easier to make a recommendation if the mechanism(s) causing the
problem can be isolated.
Reply by ●April 20, 20062006-04-20
thanks,what i was doing is the blind channel equalizer implemented in
the dsp.The alogrithm i used is the Constant Modulus Alogrithm.the
signal input is the BPSK . My tutor said to me that when checking the
results,what i only to is generate a BPSK signal with the signal
generator,and let that pass a channel,then the channel output is sent
to the DSP to equalize.But the channel property i don't know.when
simulating in matlab,i used a Ralay channel and the QPSK signal.the
chanel model likes this:h=randn(1,5)+j*randn(1,5). When the signal is
bpsk,i remove the imagination ,so the chanel becomes:h=randn(1,5).the
next step is :x=fliter(h,1,s),and x=x+randn(1,T),I think this is the
channel output,however my tutor said to me he don't know the channel.I
puzzled.how can i choose the channel model?
I don't know.
any help or suggestion appreciated.
Reply by Phil●April 21, 20062006-04-21
Have you run the BPSK scenario in MATLAB as well? If not, how do you
know what to expect? This should be the first thing you do so that you
have a basis for comparison. Further, make sure that the data and
channel are exactly the same through both the MATLAB model and the DSP.
What information are you monitoring from the DSP? Apart from the data
samples, are you observing the e(k) and f(k)?
If this comes down to a DSP debugging problem, I am of no use. I have
no experience in coding up DSPs. All my algorithms have been for
others to implement in FPGA and ASIC.
Sorry for not being more helpful.
Reply by ●April 21, 20062006-04-21
yes, i have to change my qpsk scenario to bpsks,because there are not
enough AD channels for the I and Q channel.so i change this to bpsk
scheme.i think you are quite right that make sure that the data and
channel are exactly the same through both the matlab model and the
DSP.now i have some knowledge about my bpsk scenario,and i have
realized the data flow in matlab.what i observed is the
(1/N)*sum(e(k)^2),where the N stands for the number of realization.and
also with the constellation diagrams before and after equalization.
but i have met new troubles.when i check the equipment ,i find that the
bpsk is 250 K symbol/s,while my AD conversion is 22K,maybe in the end i
have to do some bpsk modulation and demodulation in hardware or what i
In the end ,thanks sincerely for you helps,Phil.
Reply by Phil●April 24, 20062006-04-24
Sorry that I couldn't be more help.
It sounds like your sampling rates are definitely a problem. I wasn't
sure if you were actually converting your signal to analog or not. If
you can get around your rate problems, perhaps you can use the same
input to provide your QPSK I and Q samples in serial. So long as you
sort them properly in the DSP, you can then test your algorithm that
way. Just an idea.
Reply by ●April 24, 20062006-04-24
Sampling the I and Q channel serialy,that sounds like OK,but it needs
strict sampling time control.As to the specification, i don't know.
Reply by Phil●April 24, 20062006-04-24
for the time control, you can precede your data with a known data
pattern (preamble) that you lock onto. For example, have the preamble
look like "1 -1 1 -1 1 -1 1 1 -1 -1". When the data goes from nothing
to this pattern, you can make your algorithm begin the I and Q pairing.
Your tutor may be able to help you with this.