BPSK Phase and Frequency Offset Correction Using Fixed Point Algorithms

Hello,

I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro
FPGA. I will be getting IQ data on which I'll do the demodulation.
However, the IQ data has varying phase and frequency offsets which need
to be corrected before hard decision decoding can be carried out.

Has anyone implemented frequency and phase offset removal using
VHDL/fixed point algorithms? How can I approach this. Is there
somewhere I can find code for this?

Thanks and regards,

Abhishek

pygmalion wrote:
> Hello,
>
> I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro
> FPGA. I will be getting IQ data on which I'll do the demodulation.
> However, the IQ data has varying phase and frequency offsets which need
> to be corrected before hard decision decoding can be carried out.
>
> Has anyone implemented frequency and phase offset removal using
> VHDL/fixed point algorithms? How can I approach this. Is there
> somewhere I can find code for this?
>
> Thanks and regards,
>
> Abhishek

One approach that you can use is a Costas Loop, which can be
implemented in fixed point. For example, take a look at this IC:

http://www.intersil.com/cda/deviceinfo/0,0,HSP50210.html

Good luck,

John