FPGA

Hi,

I have designed a IIR filter which is formed of 14 2nd order cells.

I'd like to make it work on a FPGA. I've seen that differents forms of
cells do exist (direct, form 1, form2...).

I'd like to know which one is better for a FPGA.

Any piece of advice is welcome !

Thanks a lot for your help.

S.

What do these "different forms" look like? In terms of structure, what
is the difference between direct, form 1, form 2?

"better" in what context? Do you want the highest clock rate or
smallest amount of FPGA logic used, or easiest to design/test?

What is your sample rate?

Regards
Andrew

stephaneo@gmail.com wrote:
> Hi,
>
> I have designed a IIR filter which is formed of 14 2nd order cells.
>
> I'd like to make it work on a FPGA. I've seen that differents forms of
> cells do exist (direct, form 1, form2...).
>
> I'd like to know which one is better for a FPGA.
>
> Any piece of advice is welcome !
> 
> Thanks a lot for your help.
> 
> S.

Hi,

Differents structures are described here :
http://www.bores.com/courses/intro/iir/5_transp.htm

By "better" I meant the best way to describe the filter so that it
would be design easily for the FPGA. I've seen on the internet that
pipelined cell could be useful in designing filters for FPGAs...

I'm quite new to FPGA so any information or link is welcomed.
I'm not supposed to code it for the FPGA so I'm not quite aware with
very specific technical details. However, I've understood that,
according to the structure I choose, the design on the FPGA will be
either very complicated or more simple.

My sample rate is 18 Mhz.

Thanks a lot for your help,

Regards,

St=E9phane




Andrew FPGA wrote:
> What do these "different forms" look like? In terms of structure, what
> is the difference between direct, form 1, form 2?
>
> "better" in what context? Do you want the highest clock rate or
> smallest amount of FPGA logic used, or easiest to design/test?
>
> What is your sample rate?
>
> Regards
> Andrew
>
> stephaneo@gmail.com wrote:
> > Hi,
> >
> > I have designed a IIR filter which is formed of 14 2nd order cells.
> >
> > I'd like to make it work on a FPGA. I've seen that differents forms of
> > cells do exist (direct, form 1, form2...).
> >
> > I'd like to know which one is better for a FPGA.
> >
> > Any piece of advice is welcome !
> >=20
> > Thanks a lot for your help.
> >=20
> > S.

> By "better" I meant the best way to describe the filter so that it
> would be design easily for the FPGA. I've seen on the internet that
> pipelined cell could be useful in designing filters for FPGAs...
>
Ok, in that case why not just use the direct form. Implement each tap
multiplication using a  FPGA embedded multiplier. (look at xilinx
spartan 3 datasheet and you will see this fpga has a number of 18x18
multipliers embedded in the FPGA fabric).  Feed all 28 tap outputs back
to a 28 input adder.  I'm guessing a 28 input adder will still meet
timing with a clock rate of only 18MHz.

If the adder doesn't meet timing then I would suggest adding pipeling
as required to the adder. But because the filter is IIR and therfore
has feedback, one can't just simply add register delays to the adder.
What you could do is use a clock rate of 2x18MHz, but only enable the
tap multipliers on every 2nd cycle. This now gives your adder 2 clock
cycles to generate its sum - i.e. you can now add 1 level of pipelining
to the adder.

Disclaimer: The implementation I have described is very wasteful of
FPGA resources - but you wanted "easiest to design".

Actually, you never mentioned coefficient or sample bit widths. I think
one of the (several?) reasons filters are often implemented on
traditional DSPs using various other forms/2nd order stages etc is to
reduce the filter sensitivity to the quantisation of the coefficients.
I assume that is always going to be an issue, no matter if your
implementation is DSP or FPGA. (although I guess the FPGA does have the
advantage in that the arithmetic precision can be tailored precisely to
your needs).

Regards
Andrew

Hi andrew,

First thanks a lot for your detailed answer.

OK for the direct form I, I think I can see how to do it.

However I've made a previous study on problems that can occurs with IIR
and it appears that 2nd order cells would be the best way to implement
IIR filters. By the way as you said, quantization errors are easier to
control with such structures, that's why I would prefer to keep a 2nd
order cascade structure.

By the way, I think that, when I will have succeed in designing a
efficient 2nd order cells on the FPGA, I will be able to do any order
of filters. As I will know how much "space" a single cell takes, I will
just need to connect these cells in cascade.

Thus, I think I should look on a more complex way to design 2nd order
cell even if it's not, this time, the easiest way to design it, but the
more efficient use of the FPGA and overall a way to re-use my cells to
create new filters of higher orders.

Do you think that Direct-Form (or even tranposed) I 2nd order
structures with a pipeline at 2*Freq is the best way to achieve such a
design?

Again, thanks for your help and your time.

Stephane



Andrew FPGA wrote:
> > By "better" I meant the best way to describe the filter so that it
> > would be design easily for the FPGA. I've seen on the internet that
> > pipelined cell could be useful in designing filters for FPGAs...
> >
> Ok, in that case why not just use the direct form. Implement each tap
> multiplication using a  FPGA embedded multiplier. (look at xilinx
> spartan 3 datasheet and you will see this fpga has a number of 18x18
> multipliers embedded in the FPGA fabric).  Feed all 28 tap outputs back
> to a 28 input adder.  I'm guessing a 28 input adder will still meet
> timing with a clock rate of only 18MHz.
>
> If the adder doesn't meet timing then I would suggest adding pipeling
> as required to the adder. But because the filter is IIR and therfore
> has feedback, one can't just simply add register delays to the adder.
> What you could do is use a clock rate of 2x18MHz, but only enable the
> tap multipliers on every 2nd cycle. This now gives your adder 2 clock
> cycles to generate its sum - i.e. you can now add 1 level of pipelining
> to the adder.
>
> Disclaimer: The implementation I have described is very wasteful of
> FPGA resources - but you wanted "easiest to design".
>
> Actually, you never mentioned coefficient or sample bit widths. I think
> one of the (several?) reasons filters are often implemented on
> traditional DSPs using various other forms/2nd order stages etc is to
> reduce the filter sensitivity to the quantisation of the coefficients.
> I assume that is always going to be an issue, no matter if your
> implementation is DSP or FPGA. (although I guess the FPGA does have the
> advantage in that the arithmetic precision can be tailored precisely to
> your needs).
> 
> Regards
> Andrew

Andrew FPGA wrote:

>>By "better" I meant the best way to describe the filter so that it
>>would be design easily for the FPGA. I've seen on the internet that
>>pipelined cell could be useful in designing filters for FPGAs...

> Ok, in that case why not just use the direct form. Implement each tap
> multiplication using a  FPGA embedded multiplier. (look at xilinx
> spartan 3 datasheet and you will see this fpga has a number of 18x18
> multipliers embedded in the FPGA fabric).  Feed all 28 tap outputs back
> to a 28 input adder.  I'm guessing a 28 input adder will still meet
> timing with a clock rate of only 18MHz.

My favorite architecture for FPGA implementations of algorithms
is the systolic array.  I don't know if that is best for this problem,
but it works well for many problems.  It is then usually not so
hard to balance logic resources and clock speed to make optimal
use of the FPGA hardware.

-- glen