Hi, I have used TMS320VC5510 DSK to connect with a RF module through SPI.
I encounter a problem that using scope I can see the correct timing
of transmit data, receive data, FSX, and CLKX. But after that RRDY in
SPCR10 does not pulled high.
More detail, I try to write a register in RF module and read it back,
checking whether it is the same. I'm sure that in scope I see the writing
did happens and RF module did transmit the register data back to me. But I
did not see any change in RRDY.
In the reason I can't receive data by detecting RRDY. Does there have some
procedure that I've lost to do? I would be very appreciated for your
helping.
Regards, SJ Hsu
------------------------------------------------------------------------
ps1. The RF module works as following sequences :
------------------------------------------------------------------------
A. Write:
1. Generate FSX as slave enable, generate CLKX (SCLK).
2. First write 8 bits address.
3. Then write 8 bits data.
B. Read:
1. Generate FSX as slave enable, generate CLKX (SCLK).
2. First write 8 bits address.
3. Then RF module will reponse 8 bits data back. RF module will
not care the incoming data while it is responding.
------------------------------------------------------------------------
ps2. Following is my setting about SPI and my code.
------------------------------------------------------------------------
MCBSP_Config spi_Init = {
0x1830, /* Serial Port Control Register 1 */
0x0130, /* Serial Port Control Register 2 */
0x0040, /* Receive Control Register 1 */
0x0005, /* Receive Control Register 2 */
0x0040, /* Transmit Control Register 1 */
0x0005, /* Transmit Control Register 2 */
0x001f, /* Sample Rate Generator Register 1 */
0x2000, /* Sample Rate Generator Register 2 */
0x0000, /* Multichannel Control Register 1 */
0x0000, /* Multichannel Control Register 2 */
0x0e09, /* Pin Control Register */
0x0000, /* Receive Channel Enable Register Partition A */
0x0000, /* Receive Channel Enable Register Partition B */
0x0000, /* Receive Channel Enable Register Partition C */
0x0000, /* Receive Channel Enable Register Partition D */
0x0000, /* Receive Channel Enable Register Partition E */
0x0000, /* Receive Channel Enable Register Partition F */
0x0000, /* Receive Channel Enable Register Partition G */
0x0000, /* Receive Channel Enable Register Partition H */
0x0000, /* Transmit Channel Enable Register Partition A */
0x0000, /* Transmit Channel Enable Register Partition B */
0x0000, /* Transmit Channel Enable Register Partition C */
}
void spi_init ()
{
MCBSP_FSET(SPCR10, RRST, 0) ; // reset Rx
MCBSP_FSET(SPCR20, XRST, 0) ; // reset Tx
MCBSP_FSET(SPCR20, FRST, 0) ; // reset frame-sync logic
MCBSP_FSET(SPCR20, GRST, 0) ; // reset sample rate generator
MCBSP_config(hMcbsp0, &spi_Init) ;
MCBSP_FSET(SPCR20, GRST, 1); // enable sample rate generator
MCBSP_FSET(SPCR20, FRST, 1); // enable frame-sync logic
MCBSP_FSET(SPCR10, RRST, 1); // set Rx
MCBSP_FSET(SPCR20, XRST, 1); // set Tx
}
void spi_sw(UINT8 addr, UINT8* dataPtr)
{
//UINT16 i ;
addr = (addr << 9) | 0x0100 ;
addr = addr | (*dataPtr) ;
while (MCBSP_FGET(SPCR20,XRDY)== 0) {}
// write address to DXR
MCBSP_RSET (DXR20,0) ;
MCBSP_RSET (DXR10,addr);
//for(i = 0; i < 1000; i++) ;
}
void spi_sr(UINT8 addr, UINT8* dataPtr)
{
addr = ((UINT16)addr << 9) ;
while (MCBSP_FGET(SPCR20,XRDY)== 0) {}
// write address to DXR
MCBSP_RSET (DXR20,0) ;
MCBSP_RSET (DXR10,addr);
while (MCBSP_FGET(SPCR10,RRDY) == 0) {}
*dataPtr = MCBSP_RGET(DRR10) ;
}
UINT8 d = 0xaa ;
UINT8 r = 0x01 ;
void main()
{
spi_init() ;
spi_sw(0x01, &d) ;
spi_sr(0x01, &r) ;
printf("The returned value : %d", r) ;
}
McBSP as SPI master problem
Started by ●August 15, 2006
Reply by ●August 15, 20062006-08-15
Sorry everyone, I post this in wrong place and I can not find where to delete this post. Please recept my apology. Best Regards, SJ Hsu>Hi, I have used TMS320VC5510 DSK to connect with a RF module throughSPI.>I encounter a problem that using scope I can see the correct timing >of transmit data, receive data, FSX, and CLKX. But after that RRDY in >SPCR10 does not pulled high. > >More detail, I try to write a register in RF module and read it back, >checking whether it is the same. I'm sure that in scope I see thewriting>did happens and RF module did transmit the register data back to me. ButI>did not see any change in RRDY. > >In the reason I can't receive data by detecting RRDY. Does there havesome>procedure that I've lost to do? I would be very appreciated for your >helping. > >Regards, SJ Hsu >------------------------------------------------------------------------ >ps1. The RF module works as following sequences : >------------------------------------------------------------------------ > A. Write: > 1. Generate FSX as slave enable, generate CLKX (SCLK). > 2. First write 8 bits address. > 3. Then write 8 bits data. > B. Read: > 1. Generate FSX as slave enable, generate CLKX (SCLK). > 2. First write 8 bits address. > 3. Then RF module will reponse 8 bits data back. RF module will > not care the incoming data while it is responding. >------------------------------------------------------------------------ >ps2. Following is my setting about SPI and my code. >------------------------------------------------------------------------ >MCBSP_Config spi_Init = { > 0x1830, /* Serial Port Control Register 1 */ > 0x0130, /* Serial Port Control Register 2 */ > 0x0040, /* Receive Control Register 1 */ > 0x0005, /* Receive Control Register 2 */ > 0x0040, /* Transmit Control Register 1 */ > 0x0005, /* Transmit Control Register 2 */ > 0x001f, /* Sample Rate Generator Register 1 */ > 0x2000, /* Sample Rate Generator Register 2 */ > 0x0000, /* Multichannel Control Register 1 */ > 0x0000, /* Multichannel Control Register 2 */ > 0x0e09, /* Pin Control Register */ > 0x0000, /* Receive Channel Enable Register Partition A */ > 0x0000, /* Receive Channel Enable Register Partition B */ > 0x0000, /* Receive Channel Enable Register Partition C */ > 0x0000, /* Receive Channel Enable Register Partition D */ > 0x0000, /* Receive Channel Enable Register Partition E */ > 0x0000, /* Receive Channel Enable Register Partition F */ > 0x0000, /* Receive Channel Enable Register Partition G */ > 0x0000, /* Receive Channel Enable Register Partition H */ > 0x0000, /* Transmit Channel Enable Register Partition A */ > 0x0000, /* Transmit Channel Enable Register Partition B */ > 0x0000, /* Transmit Channel Enable Register Partition C */ >} > >void spi_init () >{ > MCBSP_FSET(SPCR10, RRST, 0) ; // reset Rx > MCBSP_FSET(SPCR20, XRST, 0) ; // reset Tx > MCBSP_FSET(SPCR20, FRST, 0) ; // reset frame-sync logic > MCBSP_FSET(SPCR20, GRST, 0) ; // reset sample rate generator > > MCBSP_config(hMcbsp0, &spi_Init) ; > > MCBSP_FSET(SPCR20, GRST, 1); // enable sample rate generator > MCBSP_FSET(SPCR20, FRST, 1); // enable frame-sync logic > > MCBSP_FSET(SPCR10, RRST, 1); // set Rx > MCBSP_FSET(SPCR20, XRST, 1); // set Tx > >} > > > >void spi_sw(UINT8 addr, UINT8* dataPtr) >{ > //UINT16 i ; > > addr = (addr << 9) | 0x0100 ; > addr = addr | (*dataPtr) ; > > while (MCBSP_FGET(SPCR20,XRDY)== 0) {} > > // write address to DXR > MCBSP_RSET (DXR20,0) ; > MCBSP_RSET (DXR10,addr); > > //for(i = 0; i < 1000; i++) ; >} > > > >void spi_sr(UINT8 addr, UINT8* dataPtr) >{ > addr = ((UINT16)addr << 9) ; > > while (MCBSP_FGET(SPCR20,XRDY)== 0) {} > > // write address to DXR > MCBSP_RSET (DXR20,0) ; > MCBSP_RSET (DXR10,addr); > > while (MCBSP_FGET(SPCR10,RRDY) == 0) {} > > *dataPtr = MCBSP_RGET(DRR10) ; >} > > > >UINT8 d = 0xaa ; >UINT8 r = 0x01 ; > >void main() >{ > spi_init() ; > > spi_sw(0x01, &d) ; > > spi_sr(0x01, &r) ; > > printf("The returned value : %d", r) ; > >} > > >
Reply by ●August 15, 20062006-08-15
SJ Hsu wrote:> Sorry everyone, I post this in wrong place and I can not find where to > delete this post. Please recept my apology.Display the post in your newsreader and use the "delete" key on your keyboard. Not every news server honors a delete request, but many do. (Yahoo might not.) Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●August 30, 20062006-08-30
Hi, have a look at MCBSP_SPCR_RINTM_RRDY bit in your serial port control register. You can view all the registers related to the mcbsp interface via code composer studio and if the DRR1/0 register isn=B4t written something is wrong with your port configuration - maybe the RRDY irq mode is enabled but the receiver is waiting for a wrong word length. I use the mcbsp with the c6 dsp family and configure these interfaces also for spi. If you use the chip support library (CSL) you get more readerfriendly code. regards stephan
