Interpolation after RRC

Hi,

In the TX side of our system, we have data being passed through the
pulse shaping filter (Root Raised Cosine) which is being sampled at 1
Mhz. It is a standard RRC...ie basic FIR structure. However, we need to
interpolate to get the sampling frequency up to 8Mhz. I have been told
my options are to use a polyhase filter structure, however it means us
going back to the drawing board.

My question is...is it possible to zero-stuff the data coming out of
the filter, by adding 7 zeros between each sample? Of course, I will
need to increase the sampling frequency to 8 Mhz.

Is this correct? Will this be the same as using a polyphase filter
structure? Many thanks for any help.

Bob Carter

<stenasc@yahoo.com> wrote in message 
news:1157748439.003567.298950@m79g2000cwm.googlegroups.com...
> Hi,
>
> In the TX side of our system, we have data being passed through the
> pulse shaping filter (Root Raised Cosine) which is being sampled at 1
> Mhz. It is a standard RRC...ie basic FIR structure. However, we need to
> interpolate to get the sampling frequency up to 8Mhz. I have been told
> my options are to use a polyhase filter structure, however it means us
> going back to the drawing board.
>
> My question is...is it possible to zero-stuff the data coming out of
> the filter, by adding 7 zeros between each sample? Of course, I will
> need to increase the sampling frequency to 8 Mhz.
>
> Is this correct? Will this be the same as using a polyphase filter
> structure? Many thanks for any help.
>
> Bob Carter

Bob,

A polyphase implementation of a FIR filter is just that .. an 
implementation.  Otherwise it has not much to do with anything about *what* 
the filter does to the signal.  It's all about *how* it does it.  So, maybe 
you should re-state your understanding and question.

Zero stuffing is the first step in interpolating - but it does no 
interpolation by itself.

I'm not sure what "going back to the drawing board" means or does not mean 
in your context.

I'm also not sure why you need to increase the (receive?) sample rate and 
how that will affect the existing RRC TX/RX structure/performance.  I think 
it might!

Fred

"Fred Marshall" <fmarshallx@remove_the_x.acm.org> writes:
> [...]
> I'm also not sure why you need to increase the (receive?) sample rate and 
> how that will affect the existing RRC TX/RX structure/performance.  I think 
> it might!

Hi Fred,

I agree that the RRC Tx/Rx structure will be changed by a new sample rate.

One good reason I've seen for increasing it beyond the required rate
is to reduce overshoot and other time-domain anomalous behaviors
in the post-processing (e.g., reconstruction) analog filter(s).
-- 
%  Randy Yates                  % "Watching all the days go by...    
%% Fuquay-Varina, NC            %  Who are you and who am I?"
%%% 919-577-9882                % 'Mission (A World Record)', 
%%%% <yates@ieee.org>           % *A New World Record*, ELO
http://home.earthlink.net/~yatescr

On 8 Sep 2006 13:47:19 -0700, stenasc@yahoo.com wrote:

>Hi,
>
>In the TX side of our system, we have data being passed through the
>pulse shaping filter (Root Raised Cosine) which is being sampled at 1
>Mhz. It is a standard RRC...ie basic FIR structure. However, we need to
>interpolate to get the sampling frequency up to 8Mhz. I have been told
>my options are to use a polyhase filter structure, however it means us
>going back to the drawing board.
>
>My question is...is it possible to zero-stuff the data coming out of
>the filter, by adding 7 zeros between each sample? Of course, I will
>need to increase the sampling frequency to 8 Mhz.
>
>Is this correct? Will this be the same as using a polyphase filter
>structure? Many thanks for any help.
>
>Bob Carter

Zero stuffing and then passing the resulting sequence through another
digital filter, running at 8MHz, that isolates only the desired
spectrum, will provide a nice interpolated/upsampled stream.

Strictly applying a FIR to the zero-stuffed sequence is
computationally inefficient, though, since it bothers to process data
which is 7/8 zeroes and will, therefore, not have much arithmetical
influence on the output.   So a polyphase structure would be a nice
implementation that helps to avoid that inefficiency.

In the old days it wasn't uncommon to make such a filter with a ROM
and a counter.

Eric Jacobsen
Minister of Algorithms, Intel Corp.
My opinions may not be Intel's opinions.
http://www.ericjacobsen.org

stenasc@yahoo.com wrote:

> Hi,
> 
> In the TX side of our system, we have data being passed through the
> pulse shaping filter (Root Raised Cosine) which is being sampled at 1
> Mhz. It is a standard RRC...ie basic FIR structure. However, we need to
> interpolate to get the sampling frequency up to 8Mhz. I have been told
> my options are to use a polyhase filter structure, however it means us
> going back to the drawing board.
> 
> My question is...is it possible to zero-stuff the data coming out of
> the filter, by adding 7 zeros between each sample? Of course, I will
> need to increase the sampling frequency to 8 Mhz.
> 
> Is this correct? Will this be the same as using a polyphase filter
> structure? Many thanks for any help.


This is not going to work. If you only stuff the data stream with zeroes 
and upscale the sample rate, that will create the number of the spectral 
aliases to your signal. That could be a disaster for the communication 
system.

How to do it right:

0. Redesign your RRC to the sample rate of 8 MHz
1. Stuff your data with zeroes before the RRC filter
2. Apply the RRC

The polyphase filter is the "scientific word" to the simple trick: since 
your data is stuffed with zeroes, there is no need to compute the filter 
taps which should do the multiplication by zero. Also, there is no need 
to store all zeroes between the data samples.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

Bob,

Maybe you'll get lucky, we'll see.

What is the bandwidth (required, actual, ... ) of the output signal?
Give as much detail as possible.

What are the frequency characteristics of the analog output signal
filter above 0.5 MHz?

Is the reason for the increased sample rate to simplify the analog
filter design?  If not, care to say why?

Dirk Bell
DSP Consultant


stenasc@yahoo.com wrote:
> Hi,
>
> In the TX side of our system, we have data being passed through the
> pulse shaping filter (Root Raised Cosine) which is being sampled at 1
> Mhz. It is a standard RRC...ie basic FIR structure. However, we need to
> interpolate to get the sampling frequency up to 8Mhz. I have been told
> my options are to use a polyhase filter structure, however it means us
> going back to the drawing board.
>
> My question is...is it possible to zero-stuff the data coming out of
> the filter, by adding 7 zeros between each sample? Of course, I will
> need to increase the sampling frequency to 8 Mhz.
>
> Is this correct? Will this be the same as using a polyphase filter
> structure? Many thanks for any help.
> 
> Bob Carter

Hi All,

Thanks for replying. As you all have correctly deduced, the upsampling
is required purely to ease the requirements for the analog filter. I
have a VHDL implementation of an RRC filter which at 1 MHz sampling
rate is very efficient in terms of space on the FPGA. However, if I use
a sampling rate of  8MHz, the number of samples required is 637, which
will not  fit on the chip. I am under time pressure, so come up with a
solution. The polyphase implementation was mentioned, but I was hoping
for a quick and dirty method instead of having re rewrite the filter
code.

Thanks
Bob


dbell wrote:
> Bob,
>
> Maybe you'll get lucky, we'll see.
>
> What is the bandwidth (required, actual, ... ) of the output signal?
> Give as much detail as possible.
>
> What are the frequency characteristics of the analog output signal
> filter above 0.5 MHz?
>
> Is the reason for the increased sample rate to simplify the analog
> filter design?  If not, care to say why?
>
> Dirk Bell
> DSP Consultant
>
>
> stenasc@yahoo.com wrote:
> > Hi,
> >
> > In the TX side of our system, we have data being passed through the
> > pulse shaping filter (Root Raised Cosine) which is being sampled at 1
> > Mhz. It is a standard RRC...ie basic FIR structure. However, we need to
> > interpolate to get the sampling frequency up to 8Mhz. I have been told
> > my options are to use a polyhase filter structure, however it means us
> > going back to the drawing board.
> >
> > My question is...is it possible to zero-stuff the data coming out of
> > the filter, by adding 7 zeros between each sample? Of course, I will
> > need to increase the sampling frequency to 8 Mhz.
> >
> > Is this correct? Will this be the same as using a polyphase filter
> > structure? Many thanks for any help.
> > 
> > Bob Carter

stenasc@yahoo.com writes:

> Hi All,
>
> Thanks for replying. As you all have correctly deduced, the upsampling
> is required purely to ease the requirements for the analog filter. I
> have a VHDL implementation of an RRC filter which at 1 MHz sampling
> rate is very efficient in terms of space on the FPGA. However, if I use
> a sampling rate of  8MHz, the number of samples required is 637, which
> will not  fit on the chip. I am under time pressure, so come up with a
> solution. The polyphase implementation was mentioned, but I was hoping
> for a quick and dirty method instead of having re rewrite the filter
> code.

Hi Bob,

As I understand your situation, there is no "quick and dirty" solution,
as you put it. There are essentially two steps you need to perform:

  1. Derive new filter coefficients,

  2. Reimplement your filter to utilize a polyphase structure.

However..., these steps are relatively simple and I don't think
they'll take a lot of time.  As Vladimir stated, "polyphase" is a
"scientific word" to a "simple trick." It should take you a short
amount of time once you get the "aha" to redesign and reimplement your
filter.

Also, although I don't know exactly how you analyzed it, I suspect
your concerns regarding "number of samples" will disappear when you
see how to implement a polyphase upsampler. Essentially the resources
are not much higher than those required for a plain old digital FIR.

There are many very knowledgable and helpful folks here - simply ask
for more help if/when you need it.
-- 
%  Randy Yates                  % "Bird, on the wing,
%% Fuquay-Varina, NC            %   goes floating by
%%% 919-577-9882                %   but there's a teardrop in his eye..."
%%%% <yates@ieee.org>           % 'One Summer Dream', *Face The Music*, ELO
http://home.earthlink.net/~yatescr

stenasc@yahoo.com wrote:
> Hi All,
> 
> Thanks for replying. As you all have correctly deduced, the upsampling
> is required purely to ease the requirements for the analog filter. I
> have a VHDL implementation of an RRC filter which at 1 MHz sampling
> rate is very efficient in terms of space on the FPGA. However, if I use
> a sampling rate of  8MHz, the number of samples required is 637, which
> will not  fit on the chip. I am under time pressure, so come up with a
> solution.

The efficient way to upsample by 8 is by upsampling by the factor of 2 
three times. You can probably use the same set of coefficients for each 
of three stages. It saves a lot of memory also.

> The polyphase implementation was mentioned, but I was hoping
> for a quick and dirty method instead of having re rewrite the filter
> code.

It depends. What is your bandwidth of interest and how many dB of the 
alias suppression do you need?

The quick and dirty way is the simplest linear interpolation of the 
missing samples. Or, perhaps, you can do it by adding one or several CIC 
stages at the output. Both ways are very cheap in the hardware.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

Randy Yates wrote:
> stenasc@yahoo.com writes:

>> I have a VHDL implementation of an RRC filter which at 1 MHz
>> sampling rate is very efficient in terms of space on the FPGA.
>> However, if I use a sampling rate of  8MHz, the number of samples
>> required is 637, which will not fit on the chip.

> Also, although I don't know exactly how you analyzed it, I suspect
> your concerns regarding "number of samples" will disappear when you
> see how to implement a polyphase upsampler.

As I understand it, for given specifications the output rate 
determines the IR length and polyphase structure won't reduce 
that...?


Martin

-- 
Quidquid latine scriptum sit, altum viditur.