I want to do a master PCI read from host memory. My test code looks
something like this...
Uint32 dsp_addr = 0x81000000;
Uint32 host_addr = 0x1ef60000;
Uint32 count = 64;
ctlreg = count << 16;
PCI_xfrConfigArgs(dsp_addr, host_addr, ctlreg, PCI_TRCTL_DEFAULT);
while (test = PCI_xfrTest())
However, the transfer never completes. Examining the registers, as
expected DSPMA is 0x81000000, PCIMA is 0x1ef60000 and PCIMC is
(64<<16)+2 (2 being the code for prefetchable read). The current
registers seem to be set to begin the transfer (i.e. CDPSA is
0x81000000, CPCIA is 0x1ef60000 and CCNT is 64). But that's how
it stays. No interrupts are generated, i.e only CFGDONE is set in
On the host side, a Linux driver has previously set up the host
registers (DSPP, etc. and mapped the prefetchable and
non-prefetchable memory windows. This works fine (the host can see
DSP memory, and interrupts can occur in both directions).
Any ideas? Does the host need to do something to allow master
reads by the DSP. Another complication is there's two identical
DSP cards in the system, is this likely to cause a problem?