Hi, When using the SG algorithm for equalizing, the error signal is computed at the end of the pll. My problem is that the pll cannot be locked before the channel is reasonably equalized. Thus, I have a "bootstrap" where the equalizer need phase information(from pll) and the pll need equalized signal in order to work properly. I still have not simulated this situation, so I need your experience here: Does such scheme suppose to work and eventually to converge, or should I use other algorithm for the equalizer, (one that is not sensitive to phase errors)? Thanks!

# interaction between bandpass equalizer and pll

tmoshe wrote:> Hi, > When using the SG algorithm for equalizing, the error signal is computed > at the end of the pll. My problem is that the pll cannot be locked before > the channel is reasonably equalized. Thus, I have a "bootstrap" where the > equalizer need phase information(from pll) and the pll need equalized > signal in order to work properly. > I still have not simulated this situation, so I need your experience > here: > Does such scheme suppose to work and eventually to converge, or should I > use other algorithm for the equalizer, (one that is not sensitive to phase > errors)? > Thanks! >Hello Tmoshe, I had this problem also. The equalizer adjustment interacts with the carrier recovery and the symbol sync recovery PLLs. Therefore the equalizer has to be on the outside of the both loops. You can do the two different things here: 1. Don't adjust PLLs directly, adjust the equalizer only. Derive the phase information from the equalizer by FFT of its coefficients. 2. Do the opposite thing: correct the phase of the equalizer coefficients in accordance with the PLL adjustment. This way the interaction of the PLLs and the equalizer will be canceled. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com

Vladimir Vassilevsky <antispam_bogus@hotmail.com> writes:> tmoshe wrote: > >> Hi, >> When using the SG algorithm for equalizing, the error signal is computed >> at the end of the pll. My problem is that the pll cannot be locked before >> the channel is reasonably equalized. Thus, I have a "bootstrap" where the >> equalizer need phase information(from pll) and the pll need equalized >> signal in order to work properly. I still have not simulated this >> situation, so I need your experience >> here: >> Does such scheme suppose to work and eventually to converge, or should I >> use other algorithm for the equalizer, (one that is not sensitive to phase >> errors)? >> Thanks! >> > > Hello Tmoshe, > > I had this problem also. The equalizer adjustment interacts with the > carrier recovery and the symbol sync recovery PLLs. Therefore the > equalizer has to be on the outside of the both loops. > > You can do the two different things here: > > 1. Don't adjust PLLs directly, adjust the equalizer only. Derive the > phase information from the equalizer by FFT of its coefficients. > > 2. Do the opposite thing: correct the phase of the equalizer > coefficients in accordance with the PLL adjustment. This way the > interaction of the PLLs and the equalizer will be canceled. > > Vladimir Vassilevsky > > DSP and Mixed Signal Design Consultant > > http://www.abvolt.comI've not tried this, but isn't another common approach to first get some equalization using CMA (hopefully enough that the timing and carrier loops pull in), then switch to your phase-dependent equalization mode. BTW, what is the "SG algorithm"? -- % Randy Yates % "Maybe one day I'll feel her cold embrace, %% Fuquay-Varina, NC % and kiss her interface, %%% 919-577-9882 % til then, I'll leave her alone." %%%% <yates@ieee.org> % 'Yours Truly, 2095', *Time*, ELO http://home.earthlink.net/~yatescr

Randy Yates wrote:>>The equalizer adjustment interacts with the >>carrier recovery and the symbol sync recovery PLLs. Therefore the >>equalizer has to be on the outside of the both loops. >> >>You can do the two different things here: >> >>1. Don't adjust PLLs directly, adjust the equalizer only. Derive the >>phase information from the equalizer by FFT of its coefficients. >> >>2. Do the opposite thing: correct the phase of the equalizer >>coefficients in accordance with the PLL adjustment. This way the >>interaction of the PLLs and the equalizer will be canceled. >> > > I've not tried this, but isn't another common approach to first > get some equalization using CMA (hopefully enough that the timing > and carrier loops pull in), then switch to your phase-dependent > equalization mode.Yes, of course. This is much simpler approach, however it works if the SNR is good enough and/or if a special sequence is provided to establish the initial lock. Otherwise the PLLs and the equalizer can wander forever. The problem happens if you have to lock on the signal starting from the arbitrary moment.> > BTW, what is the "SG algorithm"?I don't know. What do they use it for? Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com

On Tue, 12 Dec 2006 07:14:53 -0600, "tmoshe" <moshe.twitto@horizonsemi.com> wrote:>Hi, >When using the SG algorithm for equalizing, the error signal is computed >at the end of the pll. My problem is that the pll cannot be locked before >the channel is reasonably equalized. Thus, I have a "bootstrap" where the >equalizer need phase information(from pll) and the pll need equalized >signal in order to work properly. >I still have not simulated this situation, so I need your experience >here: >Does such scheme suppose to work and eventually to converge, or should I >use other algorithm for the equalizer, (one that is not sensitive to phase >errors)? >Thanks!Another option to use in this situation is a feedforward symbol timing estimator to control the PLL and not start the equalizer till PLL locks. You can also accelerate the equalizer convergence initially to get reasonably reliable estimates for PLL lock. Remember PLL doesn't need perfect decisions so you only have to open the eye a certain amount and not to the level required for your BER goals.