DPLL behavior with early-late gate timing method

Hi all!
Do you have any experience with an early-late gate timing? I've built
one and observed strange behavior in weak S/N rate. Even though, I can
observe acceptable scatterplot using Matlab function - demodulated
data have a trend to loss time base (with still proper demodulation).
Is it because of not proper phase recovery (5 to 10 degrees phase
error) or maybe these 3 points in early -late timing method is to
small and accidental noise component cause mentioned above timing
errors?

The problem does not exist in good S/N.
I use 4 sample per symbol and 3 points of time analysis (early,
prompt, late).
Thank's in advance for any helpful advices or comments.
Jarek

On Jul 5, 2:56 am, jaromicha...@interia.pl wrote:
> Hi all!
> Do you have any experience with an early-late gate timing? I've built
> one and observed strange behavior in weak S/N rate. Even though, I can
> observe acceptable scatterplot using Matlab function - demodulated
> data have a trend to loss time base (with still proper demodulation).
> Is it because of not proper phase recovery (5 to 10 degrees phase
> error) or maybe these 3 points in early -late timing method is to
> small and accidental noise component cause mentioned above timing
> errors?
>
> The problem does not exist in good S/N.
> I use 4 sample per symbol and 3 points of time analysis (early,
> prompt, late).
> Thank's in advance for any helpful advices or comments.
> Jarek

You may not realize it, but what you have is a very discretized
feedback
loop.  I would guess that your problem is that the gain of the loop or
the
bandwidth of the loop is not adjusted properly.

Your question on the effect of residual phase recovery error is
meaningless
unless you say what your modulation is.  Having 5-10 degrees of phase
error
is OK if you are using QPSK.  It is not OK if you are using 256-QAM.
Of
course, there's a lot of details omitted.

Julius

On 5 Lip, 16:41, julius <juli...@gmail.com> wrote:
> On Jul 5, 2:56 am, jaromicha...@interia.pl wrote:
>
> > Hi all!
> > Do you have any experience with an early-late gate timing? I've built
> > one and observed strange behavior in weak S/N rate. Even though, I can
> > observe acceptable scatterplot using Matlab function - demodulated
> > data have a trend to loss time base (with still proper demodulation).
> > Is it because of not proper phase recovery (5 to 10 degrees phase
> > error) or maybe these 3 points in early -late timing method is to
> > small and accidental noise component cause mentioned above timing
> > errors?
>
> > The problem does not exist in good S/N.
> > I use 4 sample per symbol and 3 points of time analysis (early,
> > prompt, late).
> > Thank's in advance for any helpful advices or comments.
> > Jarek
>
> You may not realize it, but what you have is a very discretized
> feedback
> loop.  I would guess that your problem is that the gain of the loop or
> the
> bandwidth of the loop is not adjusted properly.
>
> Your question on the effect of residual phase recovery error is
> meaningless
> unless you say what your modulation is.  Having 5-10 degrees of phase
> error
> is OK if you are using QPSK.  It is not OK if you are using 256-QAM.
> Of
> course, there's a lot of details omitted.
>
> Julius

Thank's for comment. There is QPSK of course. In fact, the problem is
smaller when I introduce more samples per symbol. But loss of time
base is still present in small S/N (now at about 5 dB less then
earlier). I am starting to look for a program code error.
Regards,
Jarek

On Jul 6, 1:38 am, jaromicha...@interia.pl wrote:

>
> Thank's for comment. There is QPSK of course. In fact, the problem is
> smaller when I introduce more samples per symbol. But loss of time
> base is still present in small S/N (now at about 5 dB less then
> earlier). I am starting to look for a program code error.
> Regards,
> Jarek

If I understand you correctly, you may have fixed the problem
when you used more samples per symbol because now effectively
your feedback loop gain in reduced.

If you want to really properly "design" your system, you have to
examine the feedback loop part:  there is a tradeoff between loop
bandwidth (i.e. how fast it will converge) and noise immunity (by
assuming that noise is white, and higher loop bandwidth means
more noise is included in the output).

I never want to assume what the modulation of a system that I
do not know is.  :^)

Julius