Hi, I really liked the VDSP and VisualAudio but I have a serious double about SHARC. In my application, the program will most likely reside on SDRAM. But SHARC has an inst cache that holds only 32 instructions. Does it mean if I have a loop has more than 32 instructions, the program sequencer will have to make multiple access to the SDRAM in a loop? If this is true, SHARC is out of my list. Thanks http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_21371_21375.pdf
SHARC, cache and sdram
Started by ●June 13, 2008
Reply by ●June 14, 20082008-06-14
"SYL" <syanli@gmail.com> wrote in message news:3f7f76d8-1f5c-451e-b0d0-b8ee90e65eda@d1g2000hsg.googlegroups.com...> Hi, > > I really liked the VDSP and VisualAudio but I have a serious double > about SHARC.VDSP is OK. Visual Audio is for those who can't live without bells and whistles.> In my application, the program will most likely reside on SDRAM. But > SHARC has an inst cache that holds only 32 instructions. Does it mean > if I have a loop has more than 32 instructions, the program sequencer > will have to make multiple access to the SDRAM in a loop? If this is > true, SHARC is out of my list.This is true. BTW, SHARC is an outdated core which never made it for the variety of reasons. In our days, it is not worth looking at. Vladimir Vassilevsky DSP and Mixed Signal Consultant www.abvolt.com
Reply by ●June 14, 20082008-06-14
On Jun 13, 5:10�pm, SYL <sya...@gmail.com> wrote:> Hi, > > I really liked the VDSP and VisualAudio but I have a serious double > about SHARC. > > In my application, the program will most likely reside on SDRAM. But > SHARC has an inst cache that holds only 32 instructions. Does it mean > if I have a loop has more than 32 instructions, the program sequencer > will have to make multiple access to the SDRAM in a loop? If this is > true, SHARC is out of my list. > > Thanks > > http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_21371_21375.pdfThe SHARC was designed to run code from internal memory (1-3mbit or RAM and /or 4mbit of ROM), all zero wait state. Just load all the code inside RAM and run from there, otherwise what you say it true.
Reply by ●June 14, 20082008-06-14
SYL <syanli@gmail.com> writes:> Hi, > > I really liked the VDSP and VisualAudio but I have a serious double > about SHARC. > > In my application, the program will most likely reside on SDRAM. But > SHARC has an inst cache that holds only 32 instructions. Does it mean > if I have a loop has more than 32 instructions, the program sequencer > will have to make multiple access to the SDRAM in a loop? If this is > true, SHARC is out of my list. > > Thanks > > http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_21371_21375.pdfI'm not sure it's so clear. ADI doesn't say how big a cache line is in the instruction cache, you haven't said how slow your memory is, and your loop size isn't clear (actually bigger is better - the worst case would be when your loop is just over 32 instructions, so you have to reload the most often). 512KB is not enough for your program / constant data? -- % Randy Yates % "The dreamer, the unwoken fool - %% Fuquay-Varina, NC % in dreams, no pain will kiss the brow..." %%% 919-577-9882 % %%%% <yates@ieee.org> % 'Eldorado Overture', *Eldorado*, ELO http://www.digitalsignallabs.com
Reply by ●June 14, 20082008-06-14
steve wrote:> On Jun 13, 5:10 pm, SYL <sya...@gmail.com> wrote: > > The SHARC was designed to run code from internal memory (1-3mbit or > RAM and /or 4mbit of ROM), all zero wait state. Just load all the code > inside RAM and run from there, otherwise what you say it true.The 1+ Mbit SHARCs are way too expensive. The reasonable SHARKs have very little of L1 memory. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●June 14, 20082008-06-14
On Jun 14, 12:57�pm, Vladimir Vassilevsky <antispam_bo...@hotmail.com> wrote:> steve wrote: > > On Jun 13, 5:10 pm, SYL <sya...@gmail.com> wrote: > > > �The SHARC was designed to run code from internal memory (1-3mbit or > > RAM and /or 4mbit of ROM), all zero wait state. Just load all the code > > inside RAM and run from there, otherwise what you say it true. > > The 1+ Mbit SHARCs are way too expensive.Compared to what? there are no alternatives to the 3mbit versions.
Reply by ●June 14, 20082008-06-14
steve wrote:>>> The SHARC was designed to run code from internal memory (1-3mbit or >>>RAM and /or 4mbit of ROM), all zero wait state. Just load all the code >>>inside RAM and run from there, otherwise what you say it true. >> >>The 1+ Mbit SHARCs are way too expensive. > > > Compared to what? there are no alternatives to the 3mbit versions.No alternatives with regard to what application? Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●June 14, 20082008-06-14
On Jun 14, 2:48�pm, Vladimir Vassilevsky <antispam_bo...@hotmail.com> wrote:> steve wrote: > >>> The SHARC was designed to run code from internal memory (1-3mbit or > >>>RAM and /or 4mbit of ROM), all zero wait state. �Just load all the code > >>>inside RAM and run from there, otherwise what you say it true. > > >>The 1+ Mbit SHARCs are way too expensive. > > > Compared to what? there are no alternatives to the 3mbit versions. > > No alternatives with regard to what application? >any application where you need 3mbit in similar form factor
Reply by ●June 14, 20082008-06-14
steve wrote:>>>>>The SHARC was designed to run code from internal memory (1-3mbit or >>>>>RAM and /or 4mbit of ROM), all zero wait state. Just load all the code >>>>>inside RAM and run from there, otherwise what you say it true. >> >>>>The 1+ Mbit SHARCs are way too expensive. >> >>>Compared to what? there are no alternatives to the 3mbit versions. >> >>No alternatives with regard to what application? >> > any application where you need 3mbitApplication like what, in particular?> in similar form factorBGA-CSP ? There are quute a few CPUs with over 2 Mbit on chip, like TMS5510, for example. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●June 14, 20082008-06-14
On Jun 14, 3:25�pm, Vladimir Vassilevsky <antispam_bo...@hotmail.com> wrote:> steve wrote: > >>>>>The SHARC was designed to run code from internal memory (1-3mbit or > >>>>>RAM and /or 4mbit of ROM), all zero wait state. �Just load all the code > >>>>>inside RAM and run from there, otherwise what you say it true. > > >>>>The 1+ Mbit SHARCs are way too expensive. > > >>>Compared to what? there are no alternatives to the 3mbit versions. > > >>No alternatives with regard to what application? > > > any application where you need 3mbit > > Application like what, in particular? > > > �in similar form factor > > BGA-CSP ? There are quute a few CPUs with over 2 Mbit on chip, like > TMS5510, for example. > > Vladimir Vassilevsky > DSP and Mixed Signal Design Consultanthttp://www.abvolt.comby form factor I mean similar device functionality, 5510 is fixed point, to begin with, there isn't anything out there to compete with a 3mbit SHARC
