I have created 32kbyte cache on dm642, and the other part is SRAM.
When i use cpu filled a part of off chip SDRAM(bufferA) with some
data, and then i use EDMA to transfer this data from bufferA to a part
of on chip SRAM(bufferB), at last i use cpu to copy this data from
bufferB to another part of off chip SDRAM(bufferC).
The algorithm was like this,
use cpu change the data in bufferA;
CACHE_wbInvL2(bufferA, buffersize, CACHE_WAIT);
CACHE_invL1d(bufferB, buffersize, CACHE_WAIT);
start EDMA transfer from bufferA to bufferB;
use cpu copy data from bufferB to bufferC;
In debugging, i have found that the data in bufferA and bufferB are
the same, but in bufferC the data have changed and some part of them
was the data that have been transferred last time.
I have changed the CACHE_invL1d() into CACHE_wbInvL2() or
CACHE_invL2(), but the phenomenon was the same.
Obviously, it is a coherence problem, Anyone who knows how to deal
with this issue?