SHARC Memory Architecture

Hi Folks,

I've been getting acquainted with the SHARC 21369 the last few days and
have some questions on its memory architecture:

  1. Is the basic idea a sort of crossbar switch in which the three
  buses, DM, PM, and IOP, are connected with the four parallel memory
  spaces ("blocks" in ADI's parlance) in as parallel a manner as
  possible? E.g., if a data value, program value, and I/O value are
  required from three different blocks, access can occur in one cycle
  (using internal memory)?

  This concept is illustrated nicely in Figure 5-1 of the "ADSP-2136x
  SHARC Processor Programming Reference", 

    http://www.analog.com/static/imported-files/processor_manuals/ADSP_2136x_PGR_rev1-1.pdf

  2. These four "blocks" or memory spaces are defined explicitly for
  internal memory (see the datasheet for the internal memory layout). It
  also appears that they are implemented via the MS{0,1,2,3} strobe
  signals in the external memory interface. Is this correct?

  3. Is it true that any of code, data, or IO can reside in any of the
  four blocks? For example, ADI suggests that internal memory block 0 be
  used for program memory and block 1 for data memory, but in reality
  these blocks can be mapped in any way desired. The only caveat is that
  if simultaneous I/O / program / data access is required within a
  block, extra cycles will be required for the access. Is this correct?

  4. What exactly is the "Super" in SHARC? Steven W. Smith (et al.) 
  states in http://www.dspguide.com/ch28/3.htm that it is the use of an
  instruction cache and I/O controller along with the data and program
  memory buses of the standard Harvard architecture.

  However, from Figure 5-1 above and the associated text, it appears
  that it is the "crossbar switching" of program, data, and IO bus
  accesses to each of the four blocks.

  Which is correct?

--Randy

-- 
%  Randy Yates                  % "How's life on earth? 
%% Fuquay-Varina, NC            %  ... What is it worth?" 
%%% 919-577-9882                % 'Mission (A World Record)', 
%%%% <yates@ieee.org>           % *A New World Record*, ELO
http://www.digitalsignallabs.com

On Jul 4, 12:10 am, Randy Yates <ya...@ieee.org> wrote:
...
>   4. What exactly is the "Super" in SHARC?

i thought the "S" stood for "Sub".  Harvard arch has a program space
and *two* data spaces (typically one for signal buffer, the other for
coefficients).  even with the cache, the first time the SHArC rips
through a loop, there are cache misses.  it's really only if you loop
a zillion times that the instruction cache competes well with a
separate program and coef space.

we'll see what Al has to say.

r b-j

robert bristow-johnson <rbj@audioimagination.com> writes:

> On Jul 4, 12:10 am, Randy Yates <ya...@ieee.org> wrote:
> ...
>>   4. What exactly is the "Super" in SHARC?
>
> i thought the "S" stood for "Sub".  Harvard arch has a program space
> and *two* data spaces (typically one for signal buffer, the other for
> coefficients).  even with the cache, the first time the SHArC rips
> through a loop, there are cache misses.  it's really only if you loop
> a zillion times that the instruction cache competes well with a
> separate program and coef space.

Hey Robert,

I think the idea is that, at least for internal memory, having four
memory spaces (ala "blocks") allows the processor to potentially grab
_three_ 32-bit values (not just two, as you would have with a two-space
standard Harvard architecture) in one clock cycle, one for the program
(PM) bus, one for the data (DM) bus, and one for I/O (IOP) bus. And
since the PM bus can double as a second data fetch bus, it means you can
grab, e.g., a coefficient and a data value in one cycle.

As you correctly point out, if the program instruction is not in cache,
then any potential second data value (e.g., a coefficient) would take a
second cycle after the instruction is fetched. But, at worst (e.g., in a
cache miss situation), the SHARC is still as good as a standard
two-space (program/data) Harvard. Or am I missing something?
-- 
%  Randy Yates                  % "Remember the good old 1980's, when 
%% Fuquay-Varina, NC            %  things were so uncomplicated?"
%%% 919-577-9882                % 'Ticket To The Moon' 
%%%% <yates@ieee.org>           % *Time*, Electric Light Orchestra
http://www.digitalsignallabs.com

>On Jul 4, 12:10 am, Randy Yates <ya...@ieee.org> wrote:
>...
>>   4. What exactly is the "Super" in SHARC?

Most microprocessors use a single address and data bus for memory access.
This type of memory architecture is called Von Neumann architecture.

Many DSPs use memory architectures that have separate
buses for program and data storage. The two buses let the DSP get a data
word and an instruction simultaneously. This type of memory architecture
is called Harvard architecture.

SHARC DSPs go a step farther by using a Super Harvard architecture.
This architecture has program and data buses, but provides a single,
unified address space for program and data storage. While the Data
Memory(DM) bus only carries data, the Program Memory (PM) bus handles
instructions or data, allowing dual-data accesses.
DSP core and I/O processor accesses to internal memory are completely
independent and transparent to one another. Each block of memory can
be accessed by the DSP core and I/O processor in every cycle&mdash;no extra
cycles are incurred if the DSP core and the I/O processor access the same
block.