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fft in verilog

Started by fren...@yahoo.com April 2, 2012
Hello

I have some questions related to verilog. How can I create a N by N matrix in verilog? In Matlab u create the signal yourself. Is it the same in verilog? cause I have to implement the overlap-save method on a FPGA board (I don't know if you have heard of it). For this, I have a signal, I have to split it in blocks of the same size and for each block to compute the FFT. I want to create a matrix that contains the twiddle factors and to multiply it with every block of samples. How can I do this in verilog since I am new in this software?

Any answer will help.
Thank you!
Hello

I have some questions related to verilog. How can I create a N by N matrix
in verilog? In Matlab u create the signal yourself. Is it the same in
verilog? cause I have to implement the overlap-save method on a FPGA board
(I don't know if you have heard of it). For this, I have a signal, I have
to split it in blocks of the same size and for each block to compute the
FFT. I want to create a matrix that contains the twiddle factors and to
multiply it with every block of samples. How can I do this in verilog since
I am new in this software?

answers:

Though two dimensional array is possible, it is easy to use single
dimensional array like reg [3:0] arr [7:0]. This will create 8 memory of 4
bits size. Suppose we need to have 3*3 matrix (which contains 8 bit data),
then we have to declare reg [7:0] mem [8:0].

Random function is available in Verilog. Algorithms like CORDIC may be used
to generate continuously varying values. We have to suitably manipulate
them.

One can write for loop, but that will be interpreted in a different way.
That is the hardware will be duplicated which is not advisable. Better to
repeat the process (multiply by twiddle factor) for every clock.

Answers are correct up to my level. However, accuracy is not assured.
Hello
>
>I have some questions related to verilog. How can I create a N by N matrix in verilog? In Matlab u create the signal yourself. Is it the same in verilog? cause I have to implement the overlap-save method on a FPGA board (I don't know if you have heard of it). For this, I have a signal, I have to split it in blocks of the same size and for each block to compute the FFT. I want to create a matrix that contains the twiddle factors and to multiply it with every block of samples. How can I do this in verilog since I am new in this software?
>
>Any answer will help.
>Thank you!

If you are new to Verilog this project is probably too large. Like any programming language, hardware description language, you need to start with simple basic examples. Learn the language and environment. Once you mastered the language or environment then a project like the one you describe can be attempted.

Otherwise use a tool like Matlabs HDL generator, Synopsys Symplify DSP, Xilinx DSP Accel, etc. These allow you to simply connect existing blocks together. No Verilog or any other HDL required. Simply build your system in an environment like Simulink.

Regards,
Chris
I agree with Chris..implementing a fft in verilog for a fresher will be
tough...One approach can be using a FPGA vendor provided FFT IP(verilog
model) and set up your project with some simple verilog code...you can use
the FFT as black box, just give some control signals and data and you will
be up and running...meanwhile you can learn verilog and then attempt the
complete fft in verilog

Abhijit
For free FFT IP cores you should check out the SPIRAL project at Carnegie Mellon: http://www.spiral.net/hardware/dftgen.html

Hello
>
>I have some questions related to verilog. How can I create a N by N matrix in verilog? In Matlab u create the signal yourself. Is it the same in verilog? cause I have to implement the overlap-save method on a FPGA board (I don't know if you have heard of it). For this, I have a signal, I have to split it in blocks of the same size and for each block to compute the FFT. I want to create a matrix that contains the twiddle factors and to multiply it with every block of samples. How can I do this in verilog since I am new in this software?
>
>Any answer will help.
>Thank you!