How to build variable-cutoff LPF with very high oversapling
I'm using a Xilinx Kintex-7 FPGA to do some low-pass filtering using System Generator/Simulink, and had a question about the architecture of the filter.
My requirements include having to use a fixed sampling rate of 80MSPS. This can't really change. I appreciate the difference b/w sample rate of the filter and the clock rate of the DSP primitives in the FPGA.
The customer wants to be able to change the cut-off frequency during runtime, going from 1kHz all the way to 8 MHz. I'd normally accommodate variable cut-off with loadable coefficients adn just change the sampling rate, but here I don't know what to do... At low cut-off rates building a filter with THAT much oversampling is not really practical, and for various reasons I can't really lower the sampling rate. What do I do?
Are there techniques, similar to superhet architectures for analog radio, to mix and move the signal to a higher bandwidth, and then filter? Such that the filter always sees the same IF band, while the VCO (e.g. its digital equivalent) tunes the mixing appropriately?
Thanks for the help!