Narrow band FIR filter

Started by rama...@gmail.com January 1, 2009
I am looking for Hardware/FPGA friendly FIR filter design.

The sampling rate is around 1250 MHz. FIR filter should be tunable with pass band of 5 MHz and cut-off of 2.5MHz on both sides.

I plan to design a low pass filter of 2.5MHz pass band and cut-off at 2.5MHZ, with attenuation becoming zero by 5MHz. This i plan shift to various frequencies my multiplying co-efficients to make it tunable. [Refer book : Understanding Digital Signal Processing by Richard G Lyons Pg. No.: 201, section 5.4]

But the number of co-efficients i am getting is too huge and hardware unfriendly. Is there any alternative algorithm that i can use. Thanks in advance.

If I understand you correctly, this sounds like a classic channelizer application. Correct me if I'm wrong.

I believe the method you are referring to in the Lyons book may involve frequency transformation which will end up being too computationally intensive for an FPGA application.

The common approach has been to use a Digital Downconverter (DDC) when a single narrowband channel is desired from a wideband source. Although other techniques may be used for larger numbers of channels.

With such a high ratio between your sampling frequency (Fs) and corner frequency (Fc) you will likely want to perform some type of decimation prior to filtering. Lowering the sample rate reduces the Fs/Fc ratio thereby reducing the number of taps required to get the shape you are after.

A Cascaded Integrator-Comb (CIC) filter is a common approach used in a DDC because it requires no multipliers and can achieve very high decimation rates with minimal complexity. You will have to do some cleanup afterwards though, which is why most DDCs follow the CIC with one or more FIR filters.

If this seems like the type of info you're looking for, answer back and I can elaborate.

In the meantime, here's a great reference for the CIC filter:


And for DDCs in general:


Thanks Bob for ur kind reply,
I went thorough Richar Lyon's wonderful book - especially the chapter
on decimation. It seems to me that given my signal at any point of
time is around 10 MHz, i can decimate the signal by 64 (1350/64 = 20
MHz), which results in much lesser hardware. It seems like the Xilinx
FIR compiler core can be used directly for this application (Though i
couldnt visualise how Xilinx implements the FIR+Decimation structure).

Thanks for all ur suggestions and links. I will go through each of them.
Vikas Akalwadi