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a simulink question about upconversion in a Com system

Started by rudy...@yahoo.com February 17, 2010
Hi,

I am trying to advance my knowledge on a QPSK communication system.
I found a simulink simulation that describes a communication system. I tried to contact the author, but I am assuming he is busy, since he didn't reply to me. So, I would appreiciate if someone can answer my question.
In case, if you would want to look at the simulink files, it is located at:
http://www.mathworks.de/matlabcentral/fileexchange/10754-qpsk-modulation-system-with-recover-loops

But I will try to explain it clearly so that it may not need to view the above simulation in simulink (Although, viewing this simulation using simulink will definately help)

what I don't understand is what is happening in one of his blocks!!
In one of his blcoks, named "Upconversion" he is receving I/Q data out of a QPSK Mapper, and then he uses a block called "Zero-Order-Hold", and then he sperates the I/Q data, and then pass each rail through a SRRC blcok, and then he multiply the I/Q rails with sin/cose oscilators, and then he mixes those two signals, and send it to the next block, which is the "AWGN Channel".

But where in the "Upconversion" path the co-called DAC is implemented?!?

Initially, I thought that the "Zero-Order-Hold" is a practical representaion for an DAC, and in a semi-efficient way performs the reconstruction filter. But, I don't understand why it is actually placed all the way in front of the "Upconversion" block, before event the SRRC? Because to my understanding the pulse shaping (SRRC) should be done in digital domain, correct?

I tried to move the "Zero-Order-Hold" block to even after the Sin/Cose oscillator, but the output eye diagram and the QPSK constellation didn't make sense.

The Author may actually be transmitting I/Q signals in Analog domain (instead of a real signal) which has not much practical preferrence, although may be enough for the sake of simulation!!!
But even if this is the case, he should have used the "Zero-Order-Hold" after the pulse shaping filter (not prior to SSRC)!!!!
Unless he is using this "Zero-Order-Hold" block for some other purpose than a representation for DAC. But if it is the case, then where in this path the actual DAC takes place?!?

please explain what is going on, or where is it that I am getting confused?
I really appreciate your answer in advance.

Thanks,
--Rudy