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New FAQ on Low Voltage Interrupt Support

Started by Michael W. Mann February 17, 2003
** New FAQ on Low Voltage Interrupt Support **
Abstract
Example code is provided for 56F801-7, 56F826-7 EVMs in support of
Low Voltage interrupts.
Problem
Do you have any example code showing how to support low voltage
interrupts (at 2.2 V and 2.7 V)?

Solution
56F8xx DSPs are protected from low voltage by two interrupts. The
first monitors the input 3.3 V to protect the I/O and peripherals
ring. It fires when 3.3 V reaches approximately 2.7 V. The second
monitors the 2.5 V that supports the core. It fires around 2.2 V.
Example code, available below, shows how to implement an interrupt
service routine to service these events.

The recommended approach is to shutdown all peripherals safely, setup
the COP timer to wake the chip up later, and then put the chip into
wait or stop mode. The example code programs the COP timer to awake
the chip in around one second.

As noted in the User's Manual chapter on clock generation, the core
cannot operate at 40 MIPs unless both interrupts are clear. So it is
important to check both the LVIS27 and LVIS22 bits in the System
Status Register before switching over from the input clock to the
output of the PLL (from 8 MHz to 80 MHz for the 56F80x and from 4 MHz
to 80 MHz for the 56F82x). Between the release of the power on reset
(POR) circuitry at 1.8 V until the release of both LVIS2x interrupts
the core can operate at 4 MHz or 8 MHz only. To operate it at 80 MHz
risks unpredictable operation of the core.

Since the PLL can take many milleseconds to lock, it is probably wise
to check the LVIS2x bits again after PLL lock. The example code does
this.

Finally, there is a window of vulnerability for low voltage events
between the time you check LVIS2x bits after PLL lock and the time
that interrupts are enabled for the first time. As long as there
isn't much going on in your code this is probably ok. Otherwise you
should move the enabling of interrupts to an earlier part of your
startup code.

Files are located at
http://groups.yahoo.com/group/motoroladsp/files/Low%20Voltage%
20Interrupt%20Examples/



The recent message from Michael Mann regarding low voltage interrupt support confused and concerned me a little bit.
 
I assume that the comment about the core not being able to run at 80MHz until the "release of both LVIS2x interrupts" refers to removal of the low voltage interrupt condition and not actual clearing of the LVIS2x bits.  My code does not clear the bits, but appears to work fine.
 
I also always assumed that the PLL would fail to lock if a low-voltage condition persisted.  The message seems to suggest that we might lock OK, but that the core might not function properly?
 
And if that's the case, how can you guarantee that in the event of a voltage drop the core is functioning well enough to service the low voltage interrupt? 
 
Finally, what is the reference to protecting the I/O and the peripherals meant to imply?  Can the part be damaged by operating below threshold?  Or will it simply not work correctly?
 
I'm curious.  Have all DSP56F8xx users implemented these elaborate low voltage checks in their software?  I suspect not.
 
-- Bill Yochum
 
 
-----Original Message-----
From: Michael W. Mann <M...@Motorola.Com> [mailto:M...@Motorola.Com]
Sent: Sunday, February 16, 2003 7:39 PM
To: m...@yahoogroups.com
Subject: [Bulk E-Mail] [motoroladsp] New FAQ on Low Voltage Interrupt Support

** New FAQ on Low Voltage Interrupt Support **
Abstract 
  Example code is provided for 56F801-7, 56F826-7 EVMs in support of
Low Voltage interrupts. 
Problem 
  Do you have any example code showing how to support low voltage
interrupts (at 2.2 V and 2.7 V)?
 
Solution   
  56F8xx DSPs are protected from low voltage by two interrupts. The
first monitors the input 3.3 V to protect the I/O and peripherals
ring. It fires when 3.3 V reaches approximately 2.7 V. The second
monitors the 2.5 V that supports the core. It fires around 2.2 V.
Example code, available below, shows how to implement an interrupt
service routine to service these events.

The recommended approach is to shutdown all peripherals safely, setup
the COP timer to wake the chip up later, and then put the chip into
wait or stop mode. The example code programs the COP timer to awake
the chip in around one second.

As noted in the User's Manual chapter on clock generation, the core
cannot operate at 40 MIPs unless both interrupts are clear. So it is
important to check both the LVIS27 and LVIS22 bits in the System
Status Register before switching over from the input clock to the
output of the PLL (from 8 MHz to 80 MHz for the 56F80x and from 4 MHz
to 80 MHz for the 56F82x). Between the release of the power on reset
(POR) circuitry at 1.8 V until the release of both LVIS2x interrupts
the core can operate at 4 MHz or 8 MHz only. To operate it at 80 MHz
risks unpredictable operation of the core.

Since the PLL can take many milleseconds to lock, it is probably wise
to check the LVIS2x bits again after PLL lock. The example code does
this.

Finally, there is a window of vulnerability for low voltage events
between the time you check LVIS2x bits after PLL lock and the time
that interrupts are enabled for the first time. As long as there
isn't much going on in your code this is probably ok. Otherwise you
should move the enabling of interrupts to an earlier part of your
startup code.

Files are located at
http://groups.yahoo.com/group/motoroladsp/files/Low%20Voltage%
20Interrupt%20Examples/


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Our designs all use an external WatchDog Timer (WDT)/Power supply monitor chip,
for reasons I have stated in earlier messages posted to this discussion group.
One of these is the following message that I posted to this group in September
of last year:
[motoroladsp] RE: Boot problem with DSP56803EVM

This WDT chip (the MAX6320PUK29CY-T) resets the DSP chip whenever the 3.3V
supply drops below approximately 2.93V, so these Low Voltage Interrupts don't
even apply to our systems. Our control systems operate under a regulatory
environment where extremely high reliability is mandatory, and failsafe design
procedures must be used, whereby a device like the DSP56F80x chip is never, ever
used to check its own operation. The internal watchdog (COP), and the internal
low-voltage monitors are two examples of this. Although they both appear to
operate properly, in our applications we cannot rely on them, if we want to have
a truly failsafe design.

Regards,

Art Johnson
Senior Systems Analyst
PMC Prime Mover Controls Inc.
3600 Gilmore Way
Burnaby, B.C., Canada
V5G 4R8
Phone: 604 433-4644
FAX: 604 433-5570
Email:
http://www.pmc-controls.com
-----Original Message-----
From: Yochum, William [mailto:]
Sent: Tuesday, February 18, 2003 8:50 AM
To:
Cc: Michael W. Mann <>
Subject: RE: [motoroladsp] New FAQ on Low Voltage Interrupt Support The recent message from Michael Mann regarding low voltage interrupt support
confused and concerned me a little bit.

I assume that the comment about the core not being able to run at 80MHz until
the "release of both LVIS2x interrupts" refers to removal of the low voltage
interrupt condition and not actual clearing of the LVIS2x bits. My code does
not clear the bits, but appears to work fine.

I also always assumed that the PLL would fail to lock if a low-voltage condition
persisted. The message seems to suggest that we might lock OK, but that the
core might not function properly?

And if that's the case, how can you guarantee that in the event of a voltage
drop the core is functioning well enough to service the low voltage interrupt?

Finally, what is the reference to protecting the I/O and the peripherals meant
to imply? Can the part be damaged by operating below threshold? Or will it
simply not work correctly?

I'm curious. Have all DSP56F8xx users implemented these elaborate low voltage
checks in their software? I suspect not.

-- Bill Yochum -----Original Message-----
From: Michael W. Mann <>
[mailto:]
Sent: Sunday, February 16, 2003 7:39 PM
To:
Subject: [Bulk E-Mail] [motoroladsp] New FAQ on Low Voltage Interrupt Support ** New FAQ on Low Voltage Interrupt Support **
Abstract
Example code is provided for 56F801-7, 56F826-7 EVMs in support of
Low Voltage interrupts.
Problem
Do you have any example code showing how to support low voltage
interrupts (at 2.2 V and 2.7 V)?

Solution
56F8xx DSPs are protected from low voltage by two interrupts. The
first monitors the input 3.3 V to protect the I/O and peripherals
ring. It fires when 3.3 V reaches approximately 2.7 V. The second
monitors the 2.5 V that supports the core. It fires around 2.2 V.
Example code, available below, shows how to implement an interrupt
service routine to service these events.

The recommended approach is to shutdown all peripherals safely, setup
the COP timer to wake the chip up later, and then put the chip into
wait or stop mode. The example code programs the COP timer to awake
the chip in around one second.

As noted in the User's Manual chapter on clock generation, the core
cannot operate at 40 MIPs unless both interrupts are clear. So it is
important to check both the LVIS27 and LVIS22 bits in the System
Status Register before switching over from the input clock to the
output of the PLL (from 8 MHz to 80 MHz for the 56F80x and from 4 MHz
to 80 MHz for the 56F82x). Between the release of the power on reset
(POR) circuitry at 1.8 V until the release of both LVIS2x interrupts
the core can operate at 4 MHz or 8 MHz only. To operate it at 80 MHz
risks unpredictable operation of the core.

Since the PLL can take many milleseconds to lock, it is probably wise
to check the LVIS2x bits again after PLL lock. The example code does
this.

Finally, there is a window of vulnerability for low voltage events
between the time you check LVIS2x bits after PLL lock and the time
that interrupts are enabled for the first time. As long as there
isn't much going on in your code this is probably ok. Otherwise you
should move the enabling of interrupts to an earlier part of your
startup code.

Files are located at
http://groups.yahoo.com/group/motoroladsp/files/Low%20Voltage%
20Interrupt%20Examples/

_____________________________________
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message will receive your answer. You need to do a "reply all" if you want your
answer to be distributed to the entire group.

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--- In , "Yochum, William" <wyochum@m...>
wrote:

> I'm curious. Have all DSP56F8xx users implemented these elaborate
low
> voltage checks in their software? I suspect not.
Even if the PLL activation in ones application does check for low
voltage, what about the bootloader? AFAIK it activates the PLL as
well (although not at 80MHz). Frank Bertling



--- In , "Yochum, William" <wyochum@m...>
wrote:
> The recent message from Michael Mann regarding low voltage
interrupt support
> confused and concerned me a little bit.
>
> I assume that the comment about the core not being able to run at
80MHz
> until the "release of both LVIS2x interrupts" refers to removal of
the low
> voltage interrupt condition and not actual clearing of the LVIS2x
bits.

The LVI bits in the System Status Register reflect the state of the
voltage compares regardless of whether you have turned on LVI
interrupts. Since these bits are sticky, i.e. once on you have to
turn them off, they can be set during power-up. This occurs between
the time the POR releases and the voltage settling at nominal 3.3 V
required by the chip.

> My code does not clear the bits, but appears to work fine.

The logic of the IO ring will work below 2.7 V, but output levels
will suffer if the peripherals aren't getting the full 3.3V
required. The User's Manual is quite explicit that the core is not
rated to run at full speed (40 MIPS or 80 MHz clock) unless both LVI
alarms are clear. You can get indeterministic behavior of the core
if you don't switch to the input clock (8 MHz or 4 MHz) when the 2.2
V interrupt or flag occurs.

> I also always assumed that the PLL would fail to lock if a low-
voltage
> condition persisted. The message seems to suggest that we might
lock OK,
> but that the core might not function properly?

Some code examples have a wait loop that can time out instead of
waiting for the PLL to lock. That may not be the case in your code.
Also, you could have a voltage sag just as the PLL locks, so it is
still a good idea to check the LVI status bits right after getting
PLL lock.

> And if that's the case, how can you guarantee that in the event of
a voltage
> drop the core is functioning well enough to service the low voltage
> interrupt?

There is sufficient headroom in the setting of the voltage interrupts
to allow for the LVI ISR to run, but you can't wait very long before
switching the clock. The example code shows this.

> Finally, what is the reference to protecting the I/O and the
peripherals
> meant to imply? Can the part be damaged by operating below
threshold? Or
> will it simply not work correctly?

Nothing bad will happen to the chip, but you will get indeterministic
behavior occasionaly if you don't support the LVI bits. The 2.7 Volt
interrupt "protects" the operation of the I/O ring. We tried to be
conservative in our design, so we designed LVI support for both 2.7 V
and 2.2 V.

> I'm curious. Have all DSP56F8xx users implemented these elaborate
low
> voltage checks in their software? I suspect not.

We tried to bring onto the DSP functions that were traditionally
implemented in other components in order to reduce part count and
system cost. Art Johnson's design implements voltage protection
using additional components, for example.

> -- Bill Yochum

> -----Original Message-----
> From: Michael W. Mann <Michael.W.Mann@M...>
> [mailto:Michael.W.Mann@M...]
> Sent: Sunday, February 16, 2003 7:39 PM
> To:
> Subject: [Bulk E-Mail] [motoroladsp] New FAQ on Low Voltage
Interrupt
> Support > ** New FAQ on Low Voltage Interrupt Support **
> Abstract
> Example code is provided for 56F801-7, 56F826-7 EVMs in support
of
> Low Voltage interrupts.
> Problem
> Do you have any example code showing how to support low voltage
> interrupts (at 2.2 V and 2.7 V)?
>
> Solution
> 56F8xx DSPs are protected from low voltage by two interrupts. The
> first monitors the input 3.3 V to protect the I/O and peripherals
> ring. It fires when 3.3 V reaches approximately 2.7 V. The second
> monitors the 2.5 V that supports the core. It fires around 2.2 V.
> Example code, available below, shows how to implement an interrupt
> service routine to service these events.
>
> The recommended approach is to shutdown all peripherals safely,
setup
> the COP timer to wake the chip up later, and then put the chip into
> wait or stop mode. The example code programs the COP timer to awake
> the chip in around one second.
>
> As noted in the User's Manual chapter on clock generation, the core
> cannot operate at 40 MIPs unless both interrupts are clear. So it
is
> important to check both the LVIS27 and LVIS22 bits in the System
> Status Register before switching over from the input clock to the
> output of the PLL (from 8 MHz to 80 MHz for the 56F80x and from 4
MHz
> to 80 MHz for the 56F82x). Between the release of the power on
reset
> (POR) circuitry at 1.8 V until the release of both LVIS2x
interrupts
> the core can operate at 4 MHz or 8 MHz only. To operate it at 80
MHz
> risks unpredictable operation of the core.
>
> Since the PLL can take many milleseconds to lock, it is probably
wise
> to check the LVIS2x bits again after PLL lock. The example code
does
> this.
>
> Finally, there is a window of vulnerability for low voltage events
> between the time you check LVIS2x bits after PLL lock and the time
> that interrupts are enabled for the first time. As long as there
> isn't much going on in your code this is probably ok. Otherwise you
> should move the enabling of interrupts to an earlier part of your
> startup code.
>
> Files are located at
> http://groups.yahoo.com/group/motoroladsp/files/Low%20Voltage%
> <http://groups.yahoo.com/group/motoroladsp/files/Low%20Voltage%>
> 20Interrupt%20Examples/ >
>
<http://rd.yahoo.com/M$3376.2803712.4220031.1927555/D=egroupweb/S
057718
>
55:HM/A14910/R=0/*http://ad.doubleclick.net/jump/N879.ameritrade.ya
hoo/B1
> 054521.29;sz00x250;adc=zhs;ord45442372412020?>
>
> <http://us.adserver.yahoo.com/l?
M$3376.2803712.4220031.1927555/D=egroupmai
> l/S=:HM/A14910/rands2403241>
>
> _____________________________________
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> this message will receive your answer. You need to do a "reply
all" if you
> want your answer to be distributed to the entire group.
>
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--- In , "frankbertling <bertling@m...>"
<bertling@m...> wrote:
> --- In , "Yochum, William"
<wyochum@m...>
> wrote:
>
> > I'm curious. Have all DSP56F8xx users implemented these
elaborate
> low
> > voltage checks in their software? I suspect not.
> Even if the PLL activation in ones application does check for low
> voltage, what about the bootloader? AFAIK it activates the PLL as
> well (although not at 80MHz).
>
> Frank Bertling

Whether you need to add LVI support to your bootloader depends on how
it is used. Many users just use the bootloader for production
programming of their modules, so they set the bootloader delay in
their applications to zero. Then the bootloader immediately launches
their application.