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Capture signal period w/ 5680x timer

Started by Steve Glow April 1, 2003
I'm trying to use a quad timer block to capture the period of an encoder
input for velocity calculation. The problem I'm having is that the
input period is quite small and frequent, so I really don't want to
service an interrupt as part of the capture.

One problem I'm having is that the capture register of the quad timer
block will only capture once without software assistance. After a
capture, it's disabled until the processor clears the IEF bit of the
status register (bit 11). Does anyone know of a way to make the capture
register keep functioning without clearing this bit? This would solve
all my problems.

Failing that, is there a way to prevent the capture from running when
the timer isn't? For example, I put the timer into mode 110 (edge of
second source triggers primary count) so that the timer starts counting
on a rising edge of the second input. I further configure the capture
to capture on the falling edge of this input. This allows me to capture
the high side period of my signal as long as the signal was low when I
configured the timer. If the signal was high however, the starting
timer value is captured on the first falling edge while the timer is
still waiting for a rising edge to start counting.

I've been working on this for a couple days, and have tried every
setting for the timers that I can think of. Has anyone been able to
capture the period of an input with minimal software overhead?

Thanks,
Steve Glow
Embedded Intelligence, Inc



Try using two timers. First timer input connects to
encoder output and counts input pulses. its output
connects to second timer input as this timer's 2nd
inputs ( primary input of 2nd timer is clock source).
So second timer can capture a period of several
encoder pulses instead of every pulse. This will
reduce you interrupt rate. but this method will cost 3
timer pins.

Charlie W. --- Steve Glow <> wrote:
> I'm trying to use a quad timer block to capture the
> period of an encoder
> input for velocity calculation. The problem I'm
> having is that the
> input period is quite small and frequent, so I
> really don't want to
> service an interrupt as part of the capture.
>
> One problem I'm having is that the capture register
> of the quad timer
> block will only capture once without software
> assistance. After a
> capture, it's disabled until the processor clears
> the IEF bit of the
> status register (bit 11). Does anyone know of a way
> to make the capture
> register keep functioning without clearing this bit?
> This would solve
> all my problems.
>
> Failing that, is there a way to prevent the capture
> from running when
> the timer isn't? For example, I put the timer into
> mode 110 (edge of
> second source triggers primary count) so that the
> timer starts counting
> on a rising edge of the second input. I further
> configure the capture
> to capture on the falling edge of this input. This
> allows me to capture
> the high side period of my signal as long as the
> signal was low when I
> configured the timer. If the signal was high
> however, the starting
> timer value is captured on the first falling edge
> while the timer is
> still waiting for a rising edge to start counting.
>
> I've been working on this for a couple days, and
> have tried every
> setting for the timers that I can think of. Has
> anyone been able to
> capture the period of an input with minimal software
> overhead?
>
> Thanks,
> Steve Glow
> Embedded Intelligence, Inc


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