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DSP56303 gone wild (PLL configuration)

Started by GuillaumeDesj June 16, 2003
Hi,

I recently noticed that when writing the value $745820 to the PCTL
(PLL config register), the DSP56303 goes completely nuts.

After loading and executing the program, all of the memory (P/X/Y)
contains the value $000089 ! This doesn't happen when i
load "simpler" values however such as $040007. (I am pretty sure that
the PCTL configuration is causing this since (when running teh step-
by-step debugger) the DSP stops its normal execution flow after
executing that line of code.

Does anybody have any idea why it would do that ?

All of the values ARE within the limits for MF( 81), PD(=8) and DF
(2). I'm using the DSP56303EVM board, so the theoretical clock
should be : 12.288*2081/(8*32).88Mhz, which is below the 100Mhz
limit...

Thanks in advance.



While the value for the PLL may theoretically be
within the limits of the device, you have not accounted
for the PCAP capacitor. The value of the capacitor on
the DSP56303EVM is not sized properly for such a large
value of MF (see the data sheet for the calculation of
PCAP). (Here I am assuming you're using an EVM, but the
same still holds for any application board.)

If you want an MF that large, you will need to change the
cap on the board. Further, since the MF is so large, you
will need to use a polystyrene, polypropylene or teflon
capacitor as noted at the end of the section on the PLL
in the DSP56300 Family Manual. I don't believe these
types of capacitors are made in surface mount, so it may
not be a trivial task to modify the EVM to accomodate a
leaded PCAP capacitor.

--david --- In , "GuillaumeDesj"
<guillaumedesj@y...> wrote:
> Hi,
>
> I recently noticed that when writing the value $745820 to the PCTL
> (PLL config register), the DSP56303 goes completely nuts.
>
> After loading and executing the program, all of the memory (P/X/Y)
> contains the value $000089 ! This doesn't happen when i
> load "simpler" values however such as $040007. (I am pretty sure that
> the PCTL configuration is causing this since (when running teh step-
> by-step debugger) the DSP stops its normal execution flow after
> executing that line of code.
>
> Does anybody have any idea why it would do that ?
>
> All of the values ARE within the limits for MF( 81), PD(=8) and DF
> (2). I'm using the DSP56303EVM board, so the theoretical clock
> should be : 12.288*2081/(8*32).88Mhz, which is below the 100Mhz
> limit...
>
> Thanks in advance.