in my aplikation i have combined 2 Timers in the following manner:
(Im Using DSP56F805,SDK and Codewarrior)
TimerB0 is in GatedCountMode and counts with IPbusfrequency upto
compvalue of 100(6 for faster pulsing) and toggles its output on
compare. Its secondary input is the output of TimerB1.
TimerB1 counts BoothEdges of the TimerB0_output,
CountOnce,CountUntilCompare, outputmode is AssertWhileActive.
Say the Comparevalue is 9. TB1OnCompareInterupt is used to indicate
the job is done.
It now seems that the TB1OnCompareInterupt is exact one TB0-Edge
earlier than the Output of TB1 is set to zero.
As long as i have a small CompValue for TB0 the Interupt latency is
big enough so the ISR start after TB1-Output is set to zero
But having a big CompValue at TB0 yields an inconsistency. My idea was to fire a exact number of pulses with TimerB0, with
different frequencies. My TB0-CompValue varies from 5 to 200.
Does Anybody have an Idea what to do?
The Erata sheet says that there is an addtional pulse at IP clk rate.
May be this is a hint for you but it wasnt for me.
Thanks in advance Yves