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I need some help designing a new board using the 56F8323. In looking for the minimum configuration for JTAG debugging I would like to confirm that the JTAG pins could just be brought out to a suitable connector with the TRST held low with a 1.5k resistor. It was suggested by someone in technical support that the onboard COP might handle the power-on reset and that no external circuitry would be needed to support the reset functions needed by the core and JTAG port. I'm not in a position to try this configuration yet and we want to move forward on the design and layout. Does anyone have information about the minimum requirements for setting up a JTAG port and chip reset? The EVM uses a quad NAND gate to coordinate a power- on reset chip, and reset switch. Is this necessary? Also for the new design The EVM drives the VREFH with a 3.0V regulated down from 3.3V. It was suggested by tech support that this is done to improve AD performance, but I have not found any hard information about this issue. The 8300UM says that this pin "may be connected to VDDA..", so what's the story here? Thanks, Rob |
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Design assistance -- JTAG and VREFH
Started by ●October 31, 2003
Reply by ●October 31, 20032003-10-31
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Rob,
I have wondered the same thing when I was working with the 827,
the EVM has the same NAND gates on the JTAG port. Then I found the 803
schematic and noticed that it did not. I also figured that the only thing
the NAND gates did was allow the board to be reset using either the button or
the JTAG port, since I never use the reset button while I was using the JTAG
port I figured it was safe to take the NANDs out. I have a board coming
back in about a week that will have this change on it. I'll let you
know how it works out.
I posted my JTAG schematic at the following link, again it's
untested, but I should know in a week if it worked or not.
http://www.pontech.com/products/DSP56Fxxx/index.html
Jacob Christ
www.pontech.com
-----Original Message----- I need some help
designing a new board using the 56F8323. From: robatacp [mailto:r...@charter.net] Sent: Friday, October 31, 2003 7:39 AM To: m...@yahoogroups.com Subject: [motoroladsp] Design assistance -- JTAG and VREFH In looking for the minimum configuration for JTAG debugging I would like to confirm that the JTAG pins could just be brought out to a suitable connector with the TRST held low with a 1.5k resistor. It was suggested by someone in technical support that the onboard COP might handle the power-on reset and that no external circuitry would be needed to support the reset functions needed by the core and JTAG port. I'm not in a position to try this configuration yet and we want to move forward on the design and layout. Does anyone have information about the minimum requirements for setting up a JTAG port and chip reset? The EVM uses a quad NAND gate to coordinate a power- on reset chip, and reset switch. Is this necessary? Also for the new design The EVM drives the VREFH with a 3.0V regulated down from 3.3V. It was suggested by tech support that this is done to improve AD performance, but I have not found any hard information about this issue. The 8300UM says that this pin "may be connected to VDDA..", so what's the story here? Thanks, Rob _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: m...@yahoogroups.com To Post: m...@yahoogroups.com To Leave: m...@yahoogroups.com Archives: http://www.yahoogroups.com/group/motoroladsp More Groups: http://www.dsprelated.com/groups.php3 ">Yahoo! Terms of Service. |
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Reply by ●October 31, 20032003-10-31
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In your schematic, it does not show that TRST is grouned or held low at power up in some way. At the very least, TRST has to be grounded at power up for the JTAG controller to come up properly in a good state. The easiest way is to tie TRST to ground through a resistor (to allow debugging) full time. Otherwise, the DSP may not power up properly and run right away. I've had several 80x EVMs that don't start running at power up unless TRST is jumpered to ground or tied with a resistor. --david --- In , "Jacob Christ" <jacob@p...> wrote: > Rob, > > I have wondered the same thing when I was working with the 827, the EVM has > the same NAND gates on the JTAG port. Then I found the 803 schematic and > noticed that it did not. I also figured that the only thing the NAND gates > did was allow the board to be reset using either the button or the JTAG > port, since I never use the reset button while I was using the JTAG port I > figured it was safe to take the NANDs out. I have a board coming back in > about a week that will have this change on it. I'll let you know how it > works out. > > I posted my JTAG schematic at the following link, again it's untested, but I > should know in a week if it worked or not. > > http://www.pontech.com/products/DSP56Fxxx/index.html > > Jacob Christ > www.pontech.com > > -----Original Message----- > From: robatacp [mailto:robjnorman@c...] > Sent: Friday, October 31, 2003 7:39 AM > To: > Subject: [motoroladsp] Design assistance -- JTAG and VREFH > I need some help designing a new board using the 56F8323. > > In looking for the minimum configuration for JTAG debugging I would > like to confirm that the JTAG pins could just be brought out to a > suitable connector with the TRST held low with a 1.5k resistor. It > was suggested by someone in technical support that the onboard COP > might handle the power-on reset and that no external circuitry would > be needed to support the reset functions needed by the core and JTAG > port. I'm not in a position to try this configuration yet and we > want to move forward on the design and layout. Does anyone have > information about the minimum requirements for setting up a JTAG port > and chip reset? The EVM uses a quad NAND gate to coordinate a power- > on reset chip, and reset switch. Is this necessary? > > Also for the new design The EVM drives the VREFH with a 3.0V > regulated down from 3.3V. It was suggested by tech support that this > is done to improve AD performance, but I have not found any hard > information about this issue. The 8300UM says that this pin "may > be > connected to VDDA..", so what's the story here? > > Thanks, Rob > > _____________________________________ > Note: If you do a simple "reply" with your email client, only the author of > this message will receive your answer. You need to do a "reply all" if you > want your answer to be distributed to the entire group. > > _____________________________________ > About this discussion group: > > To Join: > > To Post: > > To Leave: > > Archives: http://www.yahoogroups.com/group/motoroladsp > > More Groups: http://www.dsprelated.com/groups.php3 > |
