Forums

DMA configuration with DSP563xx

Started by Michael Herrscher June 3, 1999
Dear Sir,
We are working with the DSP56309 (we have moved from the 56302) and we
have some problems to configure the DMA controller. We have a complex
input signal (I and Q channels) which is sampled at a 192 kHz rate and
we would like to output this signal on our Audio interface at a 38.4 kHz

frequency. We have defined two external registers SP_I and SP_Q at
adresses Y:$ffff83 and Y:$FFFF84 for our ADCs and we use the DMA channel

0 in LINE transfer mode. The DMA0 channel must:
a) read I and Q samples each 192 kHz (IRQ_D interrupt) and store the
values in a buffer
b) generate an interrupt after 5 I and Q samples have been read
The Audio-output is done in the DMA interrupt (192 kHz/5 = 38.4 kHz)
using the ESSI0 transmitter after a simple decimation and some
filterings.

We have written some assembly-language code (see attached file) and we
have noticed that the output signal is distorted when the nops in the
lDmaInitRegisters macro are removed. Even with the nops, the output is
sometimes not correct.
Our software processes commands received from a i386ex HOST and an
example of call sequence of the different functions will be:

1. Initialise DSP registers and ESSI0 interface as described in
attached text file
2. Call SpDisableAcquisition();
3. Idle state: SpDisableAcquisition() will be called many times (at
least once)
4. DSP receives a START command: SpEnableAcquisition() is called
5. DSP receives a STOP command: goto state 3

We have the following questions:
a) when we remove the nops from the lDma0InitRegisters macro the audio
output
signal is awfully distorted because the Audio output is not done
regularly. In fact it
seems that the DMA0 interrupt does not occur regularly (38.4 kHz). Why?
b) with the instruction "jclr #M_DTD0,x:M_DSTR,*" in SpEnableAcquisition

function, we have noticed that the software loops in this instruction
for
ever. Why?
c) we have also noticed that the nops in SpDisableAcquisition function
are
necessary. With only 2 nops, the output signal is distorted too. Why 4
nops?
Because of the RTS instruction?

Thanks for your help
Regards
M. Herrscher

----------------------------------
Michael Herrscher
Kontron Instruments
Reinacherstrasse 131
4002 BASEL
Switzerland
Tel: 41 61 336 24 07
Fax: 41 61 336 22 00
Email:
----------------------------------


-------
ESSI0 configuration
Done once at startup
-------

;--------------------------------
; PORT C (ESSI0) configuration

movep #$000000,x:M_PCRC ; Reset Port C (ESSI0) Control Register

movep #$100827,x:M_CRA0 ; ESSI0 Control Register A (output Doppler data
serially)
; divide by (39+1) (((49.152 MHz)/2)/(40*16) = 38.4 kHz)
; 16 bit words

movep #$0016B0,x:M_CRB0 ; ESSI0 Control Register B
; SCD = 100
; SCKD = 1: internal clock source
; SHFD = 0: MSB first
; FSL = 01: frame sync length = bit
; SYN = 1: Synchronous mode
; MOD = 0: Normal mode
; TE = 000: transmit disable

movep #$000000,x:M_PRRC ; Port C (ESSI0) Direction Register
; all GPIO-pins are inputs (0)
movep #$00002d,x:M_PCRC ; Port C (ESSI0) Control Register
; PC0 = 1: Serial data output (right channel)
; PC1 = 0: GPIO (ODD-flag)
; PC2 = 1: frame sync (DAC load)
; PC3 = 1: serial output clock
; PC4 = 0: GPIO (FEST-flag)
; PC5 = 1: serial data output (left channel)

movep #$000000,x:M_TX00 ; move a(Q) to left AUDIO-channel
movep #$000000,x:M_TX01 ; move b(I) to right AUDIO-channel

bset #M_SSTE0,x:M_CRB0 ; ESSI0 Control Register B (see above): modify TE
bset #M_SSTE1,x:M_CRB0 ; TE = 110: transmit 0 & 1 enable -------
Macro to initialize the DMA0 channel
Called from the main-loop and DMA0 interrupt routine
-------
lDma0InitRegisters MACRO

movep #SPI_SAMP_Reg,x:M_DSR0 ; src start address
nop
nop
nop
nop
movep #gDma0Buf,x:M_DDR0 ; dst start address
nop
nop
nop
nop
movep #-1,x:M_DOR1 ; jump back to SPI_SAMP after SPQ_SAMP is
transferred
nop
nop
nop
nop
movep #1,x:M_DOR2 ; regular increment
nop
nop
nop
nop
movep #-(2*5-1),x:M_DOR3 ; Get 5 I and Q samples
nop
nop
nop
nop
movep #$000101,x:M_DCO0 ; DMA counter DCO is divided into
DCOH:DCOM:DCOL
; DCOH = 0, DCOM = 5-1, DCOL = 2-1
nop
nop
nop
nop
movep #$d61cd1,x:M_DCR0 ; DMA channel 0 config:
; DE = 1: enable DMA
; DIE = 1: DMA interrupt is generated at end of block
; DTM(2:0) = 010: line transfer triggered by request (DE cleared
at end of block)
; DPR(1:0) = 11: priority level 3 (highest)
; DCON = 0: continous mode disabled
; DRS(4:0) = 00011:IRQ_D = DMA trigger request src
; D3D = 1: 3-dim mode
; DAM(5:3) = 001: src addressing mode = 2D with offset DOR1
; DAM(2) = 1: dst addressing mode = 3D with offsets DOR2:DOR3
; DAM(1:0) = 01: counter mode D: DCOH = DCO(23:18), DCOM =
DCO(17:6), DCOL = DCO(5:0)
; DDS(1:0) = 00: dst memory space = x
; DSS(1:0) = 01: src memory space = y
nop
nop
nop
nop
ENDM
-------
Enable acquisition
Done upon user action
-------
FSpEnableAcquisition

; register save
move m0,y:(r6)+

; function body

; Initialise some variables

; Initialise DMA registers
jclr #M_DTD0,x:M_DSTR,*
lDma0InitRegisters

nop
nop
nop
nop

bset #M_D0L0,x:M_IPRC ; enable DMA0 interrupt at level 3 (highest
priority)
bset #M_D0L1,x:M_IPRC

; register restoration
move y:-(r6),m0

rts
-------
Disable acquisition (refer to ES84 chip erratum)
Done upon user action
-------
FSpDisableAcquisition
bclr #M_DIE,x:M_DCR0 ; clear DIE bit in DCR0
bclr #M_DE,x:M_DCR0 ; clear DE bit in DCR0 to stop DMA0
bclr #M_DE,x:M_DCR0 ; clear DE bit in DCR0 to stop DMA0
nop
nop
nop
nop
rts
-------
DMA0 channel interrupt routine
Called after 5 I & Q samples are transferred
-------
SpDecimByXIrqHandler

;--------------------------------
; Reprogram DMA0 channel (due to chip errata ES46)
; Might be eliminated for a newer silicon
nop
nop
nop
jclr #M_DTD0,x:M_DSTR,*
lDma0InitRegisters

;-------------------------- Save registers

;-------------------------- Dump DMA buffer -> circular input buffer

;-------------------------- Decimate input values

;-------------------------- Audio wall filter, PRF rejection, lowpass

;-------------------------- Output I value
movep a1,x:M_TX00

;-------------------------- Audio wall filter, PRF rejection, lowpass

;-------------------------- Output Q value
movep a1,x:M_TX01

;-------------------------- Restore registers

rti