Loganathan (@LoganathanN)
Hello All,I need to implement a channel power measurement logic for the following reason. Actual problem statement is to detect the COMM radio activity (which last...
Hello MarkSitkowskiThanks for your reply. I think that your hidden picture meant to say the SNR (or Noise floor) is same for both 512 point DFT and 8192 (512 + 7680...
Hi all,I hope that you're all fine and doing great. I'm planning to implement a FSK demodulator for my thesis in FPGA. System requirements are given below.* Modulation...
Hello,Thanks for the reply. The auto-correlation matrix in the transmitter is a wide band signal. So I can't have a separate narrow band filter for the strong signal.RegardsLoganathan...
Hello all,I'm using an auto-correlation based frequency recovery algorithm in the receiver to extract and correct the carrier frequency offset between the transmitter...
Hi All,
I need some clarification in implementing Single Carrier Block Modulation. Especially in the receiver section. Transmit structure is consisting of 1 Pilot...
Hi Tim Wescott,Thank you for your interest shown in my query. I've gone through the slides. Correlative Interferometry will work fine. But I'm trying to unwrap the...
Hi all,I'm looking forward to implement a Direction finding algorithm for a Circular array antenna structure for 0 to 360 degree. I'm having uniformly placed 5...
Hi all,I'm just looking in a small algorithm development where I've to find out CW Signals in my band of interest 140 - 180MHz (40MHz BW). I'm using 1024 point FFT...
Hi Markus,Thanks for your interest towards my query. Surely I'll workout this and come back soon with the results.Thanks Loganathan N
Hi,Thanks for your reply. Actually the band of interest will be 136MHz to 176MHz (40MHz BW). Within this 99 diifferent channels are operating with the channel spacing...
Hi all,I'm just trying to demodulate the GMSK signal with BT of 0.5 and 224Kbps data rate. Hence F1 - F2 = 112KHz. I'm little bit confused on this demodulation algorithm....
Hi Olivier,Kindly take a look at my detailed answer & suggest me for any better way of implementation. Thanks for your interest showing on my queries. Thanks...
Hi Mark,Thanks for the detailed answer. Your suggestions are really perfect for multiplier & memory(DDS) less frequency shifting. Now I've came up with some...
Hi Oliviert,Yes you're right, we're using Ultrascale FPGA. At what rate I've to design my Half band filter, either at 3.2GHz or 400MHz. What do you mean by SSR...
Hi allI'm going to work with high speed ADC in my upcoming project. I'm having 4 ADC channels with 3.2GHz sampling rate interfaced with FPGA. I'm getting 40 samples...
HiSpetcavich & Rick Lyons both are correct if you are interpolating your signal by inserting zeros. If you are using anything like CIC filter for interpolaton,...
Hi Rick Lyons,In my original post, that spectral plot has taken from spectrum analyzer, not from any software or any simulation.In your MATLAB code, just increase...
Hi Rick Lyons,Yes, You're right regarding the frequency resolution. It won't make any sense related to Digital Analog Converter(DAC). My doubt is, How can we conform...
Hi JohnI've agreed with your suggestion. In Xilinx DDS IP
Core, Phase dithered DDS option is available, that will introduce some
random noise with the output of...
Hi,With MATLAB Spectrum Plot, How can we confirm that there is no spurious due to that envelope?Because with MATLAB FFT Function, we'll get the same envelope for...
Hi Rick Lyons,1. I meant that discrete time waveform generation in FPGA should be within + or - 10Hz frequency resolution.2. I've worked in MATLAB System Generator...
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