interaction between bandpass equalizer and pll

Started by tmoshe in comp.dsp11 years ago 4 replies

Hi, When using the SG algorithm for equalizing, the error signal is computed at the end of the pll. My problem is that the pll cannot be locked...

Hi, When using the SG algorithm for equalizing, the error signal is computed at the end of the pll. My problem is that the pll cannot be locked before the channel is reasonably equalized. Thus, I have a "bootstrap" where the equalizer need phase information(from pll) and the pll need equalized signal in order to work properly. I still have not simulated this situation, so I need your experience...


interaction between bandpass equalizer and pll

Started by tmoshe in comp.dsp11 years ago 1 reply

Hi, When using the SG algorithm for equalizing, the error signal is computed at the end of the pll. My problem is that the pll cannot be locked...

Hi, When using the SG algorithm for equalizing, the error signal is computed at the end of the pll. My problem is that the pll cannot be locked before the channel is reasonably equalized. Thus, I have a "bootstrap" where the equalizer need phase information(from pll) and the pll need equalized signal in order to work properly. I still have not simulated this situation, so I need your experience...


Use DSP to implement fractional N PLL

Started by ghlou in comp.dsp11 years ago 2 replies
PLL

Hi all, I have an integer PLL and DSP in my system, I want fine resolution (a fraction of the PLL step size). Is possible to just use the DSP...

Hi all, I have an integer PLL and DSP in my system, I want fine resolution (a fraction of the PLL step size). Is possible to just use the DSP to adjust the reference frequency instead of using a fractional-N PLL chip? Thanks Guang


PLL with external feedback at 622.08

Started by Anonymous in comp.dsp9 years ago 3 replies
PLL

Hi All I’m going to design a PLL for the frequency of 622.08MHz. This PLL should support external feedback. I’ve looked for such PLL muck but...

Hi All I’m going to design a PLL for the frequency of 622.08MHz. This PLL should support external feedback. I’ve looked for such PLL muck but I haven’t found . What shall I do if such a PLL doesn’t exist? I know that there is many “phase and freq. detector” and VCXO from different vendors but I don’t know how to design Loop filter and charge pump. Is there any IC that integra


When is a fractional-N PLL needed?

Started by gretzteam in comp.dsp7 years ago 9 replies
PLL

Hi, I'm trying to understand when a fractional-N PLL is required. I'm doing this in an FPGA so it's an ADPLL, but I think my questions are basic...

Hi, I'm trying to understand when a fractional-N PLL is required. I'm doing this in an FPGA so it's an ADPLL, but I think my questions are basic enough that it applies to any PLL. When using a basic PLL topology: ref -> PFD -> LPF -> NCO -> output | | |


MSK demodulation using PLL

Started by Anonymous in comp.dsp11 years ago 1 reply

Can I implement a MSK demodulator using PLL? Basically I want to demodulate MSK using FM demodulator IC. The IC uses a PLL for...

Can I implement a MSK demodulator using PLL? Basically I want to demodulate MSK using FM demodulator IC. The IC uses a PLL for FM demodulation. What are the drawbacks in using PLL ( if I can use one ) as compared to coherent demodulator with carrier recovery? Thanks ~ Kaushal


PLL Basics

Started by Michelot in comp.dsp9 years ago 33 replies
PLL

Bonjour, I'd like to understand what is globally a bandwidth PLL. I know that a PLL uses in internal low pass filter (numerical). But, if...

Bonjour, I'd like to understand what is globally a bandwidth PLL. I know that a PLL uses in internal low pass filter (numerical). But, if we take a PLL as a black box, in relation with the input reference timing, is it again a low pass filter with just a high cutoff frequency, or a bandpass filter with both a low and high cutoff frequencies ? Thanks for some words about this. Best re...


What does unit/rad mean in DPLL phase detector?

Started by fl in comp.dsp4 years ago 3 replies

Hi, This question is about digital PLL design. The DPLL is in fact a software PLL according to some PLL's definition. It calculates the phase...

Hi, This question is about digital PLL design. The DPLL is in fact a software PLL according to some PLL's definition. It calculates the phase error with hardware. This phase error passes through a typical digital PI filter, arrives at a NCO. I want to design a similar PLL. Before implementation, I would like to simulate this PLL in Matlab. The questions are about the phase detect


Re: Software PLL (SPLL)

Started by Terry Given in comp.dsp12 years ago

Ron N. wrote: > Tim Wescott wrote: > > > Implementing a PLL in software uses the same basic theory as > > implementing a PLL in hardware --...

Ron N. wrote: > Tim Wescott wrote: > > > Implementing a PLL in software uses the same basic theory as > > implementing a PLL in hardware -- you compare your synthesized signal to > > a reference, generate a phase difference, then servo the frequency of > > your synthesized signal to your reference. > > > Why? Isn't a software PLL just a forward interpolator. Why not just > estimate (statist


Re: Software PLL (SPLL)

Started by Ron N. in comp.dsp12 years ago

Tim Wescott wrote: > Implementing a PLL in software uses the same basic theory as > implementing a PLL in hardware -- you compare your...

Tim Wescott wrote: > Implementing a PLL in software uses the same basic theory as > implementing a PLL in hardware -- you compare your synthesized signal to > a reference, generate a phase difference, then servo the frequency of > your synthesized signal to your reference. Why? Isn't a software PLL just a forward interpolator. Why not just estimate (statistical, FFT, phase vocoder or oth


Re: Software PLL (SPLL)

Started by Ron N. in comp.dsp12 years ago

Terry Given wrote: > Ron N. wrote: > > Tim Wescott wrote: > > > Implementing a PLL in software uses the same basic theory as > > >...

Terry Given wrote: > Ron N. wrote: > > Tim Wescott wrote: > > > Implementing a PLL in software uses the same basic theory as > > > implementing a PLL in hardware -- you compare your synthesized signal to > > > a reference, generate a phase difference, then servo the frequency of > > > your synthesized signal to your reference. ... > > Why? Isn't a software PLL just a forward interpolator. Why no


Software PLL - the math that i did looks too simple to be true - please confrim

Started by mir_aculous in comp.dsp7 years ago 13 replies

Dear all, After taking your advice on looking into application notes etc for PLL I think i finally understood the theory behind a PLL and I think...

Dear all, After taking your advice on looking into application notes etc for PLL I think i finally understood the theory behind a PLL and I think I can write an algorithm now. I just wanted to share what I learned and if there is any mistake in my understanding then please correct me. I will start writing the algorithm as soon as I finish this post. Looking into Motorola 4046's app note and a ...


Software PLL - Help!

Started by tomz in comp.dsp10 years ago 5 replies

OK, I've been fighting with the code for a software PLL for a week now. I'm sure I'm missing something simple, but I haven't been able to...

OK, I've been fighting with the code for a software PLL for a week now. I'm sure I'm missing something simple, but I haven't been able to figure it out. For the code, my starting point is C R Bond's implementation (http://www.crbond.com/pll.htm) based on Best's DPLL-like SPLL (section 5.3.2 in the 4th edition). I have converted this to C#. The only other change I made was to replace the refe...


FM demod using PLL

Started by lightmetal in comp.dsp14 years ago 19 replies

I am looking for an example of using a software pll for demod of FM. I tried the other fm demod routines (arctan, differentiator) and...

I am looking for an example of using a software pll for demod of FM. I tried the other fm demod routines (arctan, differentiator) and think there could be an improvement using a software pll. I found some matlab code posted by Tom ? that works on his data (generated by matlab) but fails on mine. I think it has something to do with the hz/volt or modulation index. I am also not exactly su...


Discrete time PLL (Digital PLL, DPLL)

Started by Emanuel Landeholm in comp.dsp14 years ago 3 replies
PLL

comp.dsp, I need a robust*, free discrete time PLL algorithm, and I haven't had much luck searching the net. Pointers...

comp.dsp, I need a robust*, free discrete time PLL algorithm, and I haven't had much luck searching the net. Pointers anyone? TIA, Emanuel Landeholm *Must work with reasonably non-sinusoidal signals (harmonic distortion) and reasonably aliased (inharmonic distortion, pseudo periodic) input.


Loop Bandwidth and PLL understanding

Started by aizza ahmed in comp.dsp6 years ago 8 replies

Hello Everybody, Thanks to all experts, i am learning a lot from this group. after studying good amount of literature, i see that the...

Hello Everybody, Thanks to all experts, i am learning a lot from this group. after studying good amount of literature, i see that the terminology Loop Bandwidth is more applicable to Analog PLL. Say in Costal PLL, the more accurate terminologies are Cut-Off frequency of the LPFs and the quiescient frequency of the NCO. kindly confirm ?? Also i see in matlab simulations on central ...


Phase/Amplitude detector in PLL

Started by Vladimir Vassilevsky in comp.dsp7 years ago 21 replies
PLL

In the classic treatises on PLL, they consider phase detectors as purely phase detectors, i.e. devices which output the phase of the signal...

In the classic treatises on PLL, they consider phase detectors as purely phase detectors, i.e. devices which output the phase of the signal regardless of the instant magnitude of the signal. I wonder if there could be possible to improve the SNR of the PLL by considering the magnitude also. Do you know a book or article which talks about that? VLV


Re: Software PLL (SPLL)

Started by Mark in comp.dsp12 years ago

As long as we are on the subject of software PLLs, I have a question.... A software PLL is based on an NCO and an NCO unlike a VCO has a...

As long as we are on the subject of software PLLs, I have a question.... A software PLL is based on an NCO and an NCO unlike a VCO has a minimum step size so it can only achieve a number of discrete frequencies, i.e. the output frequency is quantized. Now if the input to the PLL is an arbitrary frequency the NCO will not be able to lock exactly to the correct frequency but only to the nea...


All Digital PLL Design

Started by rickman in comp.dsp8 years ago 11 replies

I posted a message a couple of months ago on a PLL I am working on, but I can't continue that thread. The circuit is using a PLL to generate an...

I posted a message a couple of months ago on a PLL I am working on, but I can't continue that thread. The circuit is using a PLL to generate an output clock which is a integer ratio multiple of the input clock. The purpose is to pull data out of a FIFO at the same rate it is going in and to keep a fixed amount of data in the FIFO while driving the output which is an interleave circuit. So ...


Re: Software PLL (SPLL)

Started by Ron N. in comp.dsp12 years ago

Ken Smith wrote: > In article , > Ron N. wrote: > > Tim Wescott wrote: > > > Implementing a PLL in software uses the same basic...

Ken Smith wrote: > In article , > Ron N. wrote: > > Tim Wescott wrote: > > > Implementing a PLL in software uses the same basic theory as > > > implementing a PLL in hardware -- you compare your synthesized signal to > > > a reference, generate a phase difference, then servo the frequency of > > > your synthesized signal