C6713: QDMA and EDMA chaining

Started by Bernhard Gustl Bauer in comp.dsp13 years ago 2 replies

Hello, is it possible to chain QDMA and EDMA? I want EDMA to reload SRC and DST of QDMA. What I want to do is transfer 134 blocks of 8...

Hello, is it possible to chain QDMA and EDMA? I want EDMA to reload SRC and DST of QDMA. What I want to do is transfer 134 blocks of 8 words to different locations in memory. There is no patern in this blocks so can not use a 2D EDMA. So I configured QDMA to transfere 8 words and chained it to a EDMA. EDMA reloads SRC and DST and should trigger a new QDMA cycle. The 1st QDMA is tr...


Can QDMA be paused by the CPU (TI, 67xx)

Started by howy in comp.dsp13 years ago 2 replies

Hi folks, On a TI c6713 DSP I have the QDMA sending a few Mbytes per second (a few kbytes per transfer) of data from SDRAM to a hard...

Hi folks, On a TI c6713 DSP I have the QDMA sending a few Mbytes per second (a few kbytes per transfer) of data from SDRAM to a hard drive periodically. Each QDMA data transfer lasts longer than a few audio processing interrupts. The audio processing interrupt is a great time for this transfer to happen since SDRAM is hardly accessed and therefore the QDMA transfer happens almost for fr...


How to use couple many QDMA's?

Started by ramaa in comp.dsp10 years ago 1 reply

Hi everyone, I am working in developing AV player in DM642 environment and Using the QDMA option for moving pixel data between onchip and...

Hi everyone, I am working in developing AV player in DM642 environment and Using the QDMA option for moving pixel data between onchip and external memory.The QDMA deals with now 8 bit element size.I had seen some where in the TI manuals that use of 32 bit element size will lead to optimization.But all is needed to transfer 8 bit pixel data for processing..Then how to optimize the data transfe...


How to optimize with QDMA in DM642?

Started by ramaa in comp.dsp10 years ago

Hi everyone, I am working in developing AV player in DM642 environment and Using the QDMA option for moving pixel data between onchip and...

Hi everyone, I am working in developing AV player in DM642 environment and Using the QDMA option for moving pixel data between onchip and external memory.The QDMA deals with now .. 8 bit element size.I had seen some where in the TI manuals that use of 32 bit element size will lead to code ptimization.But all is needed to transfer 8 bit pixel data for processing..Then how to optimize the dat...


QDMA in C64xx is offset by 1 byte from the desired location

Started by Anonymous in comp.dsp9 years ago 5 replies

Hi, I am using QDMA to transfer a chunk of 16 16-byte words from internal memory to SDRAM. The problem is that when the source address is...

Hi, I am using QDMA to transfer a chunk of 16 16-byte words from internal memory to SDRAM. The problem is that when the source address is odd- numbered, the QDMA copies data from one location prior to the desired source addr. For e.g. if the source memory is like this (Little Endian): Addr Data 0x3 0xAABB 0x5 0xCCDD 0x7 0xEEFF If I want to copy 2 ...


QDMA of TI DM642 DSP !! Please!!

Started by rhodesn in comp.dsp13 years ago 1 reply

I want to use QDMA of DM642 in my mpeg4 decoder. My task is : copy 352 element to 352*288 element, and per line is same ,that is 1-D to 2-D ....

I want to use QDMA of DM642 in my mpeg4 decoder. My task is : copy 352 element to 352*288 element, and per line is same ,that is 1-D to 2-D . In fact my destination is image_setedges() in xvid CODEC. Because this module is very time-consuming. Please help me!! thanks !!!


TMS320DM642 8bit QDMA transfers and subsampling

Started by Mark Robinson in comp.dsp12 years ago 5 replies

Hi all. I'm using a DM642 to capture a PAL frame from a video port as 8 bit YCbCr. I want to subsample this frame by half, but I can't use...

Hi all. I'm using a DM642 to capture a PAL frame from a video port as 8 bit YCbCr. I want to subsample this frame by half, but I can't use the video port scaler because I need the full frame too. I tried this using 8 bit QDMA transfers set up as indexed source/incremented dest. The problem is that this is the probably the most inefficient use of the EDMA engine possible, and the whole th...


DAT module in CSL 3.0 (EDMA 3)

Started by moshe shimoni in comp.dsp11 years ago

Hi, I have seen that the DAT module API has changed in the new CSL (v3.0). As far as I saw, it's not possible to have more than 1 transfer at...

Hi, I have seen that the DAT module API has changed in the new CSL (v3.0). As far as I saw, it's not possible to have more than 1 transfer at a time. When you open the module with DAT_open you have to define on which QDMA channel the transfer will be triggered, and which tcc you get. There's no more DAT_CHAANY as it was before. I do some transfers and get the same xfr_id. So the question is,...


6711 dsk bootloader

Started by Suodatin Pussi in comp.dsp13 years ago 7 replies

Hi, Has any of you already successfully written a bootloader for the 6711 dsk? I'm trying to find out what my options are. At the end I need...

Hi, Has any of you already successfully written a bootloader for the 6711 dsk? I'm trying to find out what my options are. At the end I need an interrupt vector table at 0x00 and a lot of fast internal ram for my data (filters), the same location where the bootloader will be loaded at the bootsequence (first 64 k). btw the bootsequence is an action of the qdma which copies the first 64k f...


Cache problems on TI C6416 DSP

Started by gie78 in comp.dsp11 years ago 2 replies

Hi all, I am using the C6416 fixpoint dsp from TI. My currently usecase is as follow. The SDRAM is connected to EMIFA CE0. A Blockram is...

Hi all, I am using the C6416 fixpoint dsp from TI. My currently usecase is as follow. The SDRAM is connected to EMIFA CE0. A Blockram is connected on EMIFA CE1. The L2 memory is configured is 256K Cache, that means Cache for CE0-Space is enabled. Now my application works with a buffer which is situated in the SDRAM. This buffer is served by a qdma transfer from the Blockram. To guarantee ...