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Hi, I tried to simulate a communication through SPORT 1A channels, in chained DMA mode(multichannel operation). my orginal intention is communicate to the codec (tlv320aic27 frm texas instruments) through SPORT of ADSP21065L in multichannel mode. Some of my configurations are as follows 32 bit length, 5 channel for transmission and 32bit length 3 channel (for all valid 96 bits-16+20+20+20+20 included) for reception. Multichannel operation with no companding. TX interrupt is used for data processing and RX interrupt is disabled. For simulation purpose, the sport takes data from a DAT file and the outgoing data is written to another DAT file. The TCB' s are looks as follows // Set up tansmit DMA tcb xmit_tcb[7] = (int)tx_buff; // internal dma buff address xmit_tcb[6] = 1; // internal modifier xmit_tcb[5] = 5; // internal count xmit_tcb[4] = (((int)&xmit_tcb[7])&0x0001ffff)|0x00020000; // set the pci bit on transmit block chain pointer xmit_tcb[3-0] = 0; // Set up receive DMA tcb rcv_tcb[7] = (int)rx_buff ; // internal dma buff address rcv_tcb[6] = 1; // internal modifier rcv_tcb[5] = 3; // internal count rcv_tcb[4] = (((int)&rcv_tcb[7])&0x0001ffff); // receive block chain pointer rcv_tcb[3-0] = 0; On simulation i encounered the following problems. if i writes the address directly in to the corresponding loacation for the transmit and receive TCB loacations(as shown above), i am loosing first incoming data. and the first outgoing data is some garbage value. the second and third data is read properly and written back to DAT file. this procedure is repeated in following DMA operations. when looking the DMA index registers on simulation after loading the TCB, the value of the index reg(IIR1A) is 0xC010 (the internal absolute address for the rx_buff, not offsetted one) and after the first 32bit received the IIR1A is changed to 0x4011 (0xC010-0x8000+1). the first data read is not entered in to the rx_buff location. it is missing. (i don't know how to read this value from RX buffer on simulation time). the second and third channels (32bit data) are reading properly and put it in to the rx_buff+1 and rx_buff+2 location( at this time index reg is 0x4011 and 0x4012 respectively). If i changed the transmit and receive TCB's as rcv_tcb[7] = (int)rx_buff - 0x8000 ; // internal dma buff address xmit_tcb[7] = (int)tx_buff - 0x8000; // internal dma buff address on compilation the VDSP shows a warning as ".\codecv2v1.c", line 78: warning #170-D: pointer points outside of underlying object rcv_tcb[7] = (int)rx_buff - 0x8000; // internal dma address same warning for the transmit TCB also. but on simulation, the value of the IIR1A after the first TCB load is 0x4010(instead of 0xC010 in earlier case) and the value is read from the incoming file properly and is written back to another file correctly. The second and third data reading time, the index reg is 0x4011 and 0x4012 respectively. The ISR is written in assembly and registered from C. i checked the timing constraint. it is not so good. but it should work with the present situation. VDSP version is 2.0(30 days trial version) and IDDE version 5.0.0.2 Some specific issues regarding hardware from the Codec(tlv320aic27 ) datasheet the typical value for the t (SYNC_HIGH) is 1.3microsecs (as per AC'97 TAG phase time). and they are not mentioned abt any Minumum value for the t(SYNC_HIGH) on the spec. Here i am using the RFS1 as SYNC for the codec. I think it will be remain high only for one clock cycle. the external clock for the sport is 12.888MHz. so the one clock period is 81.4ns. is it make any problems with the design. (also the codec samples the frame sync only for the first cycle prior to the transmission of the MSB of the TAG phase time slot, some where i read like that). please help me to clear the above. regards ajith |
DMA Controller Problem On Simulation
Started by ●December 10, 2002
