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I'm looking for a C source example that shows interrupt processing
for an external device. In particular, how do I disable interrupts in C for a device so that I can safely manipulate related data structures (eg. buffer pointers)? Is there some way to save and restore the interrupt state? On an 80186, I can use the sequence ; save interrupt enable state (part of machine flags) on stack pushf cli ; disable interrupts ... ; work with interrupts disabled popf ; restore interrupt enable state This works in subroutines that might be called from either interrupt or background code. (I use inline assembler and hide these behind macros for portability.) Is there an equivalent SHARC idiom? -- Ken mailto: http://www.sewingwitch.com/ken/ http://www.215Now.com/ |
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Canonical SHARC interrupt disabling
Started by ●August 16, 1999
Reply by ●August 17, 19991999-08-17
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hello, On Mon, 16 Aug 1999, Ken wrote: > I'm looking for a C source example that shows interrupt processing for > an external device. In particular, how do I disable interrupts in C for > a device so that I can safely manipulate related data structures (eg. > buffer pointers)? > > Is there some way to save and restore the interrupt state? On an 80186, > I can use the sequence > > ; save interrupt enable state (part of machine flags) on stack > pushf > cli ; disable interrupts > ... ; work with interrupts disabled > popf ; restore interrupt enable state > > This works in subroutines that might be called from either interrupt or > background code. (I use inline assembler and hide these behind macros > for portability.) > > Is there an equivalent SHARC idiom? i am not sure if i got completely what you want, but for disabling and enabling interrupts globally, you can use: asm("#include <def21060.h>"); ... asm("bit clr MODE1 IRPTEN;"); // disable irq's globally // interrupt-sensitive code here asm("bit set MODE1 IRPTEN;"); // enable irq's globally normally this should be enough to provide an "interrupt-free" part of code. i don't recall what the interrupt enable state on the x86 is exactly. the sharc has a separate interrupt enable register (IMASK) and a separate interrupt latch register (IRPTL), which are not affected by the above instructions. and unless there occurs more than one interrupt of the same type, you don't even loose an interrupt, the irq request is stored (and might be cleard manually) in IRPTL. note: when compiling with optimization, the inline-assembler instructions might be moved by the optimizer. one way is to write "asm volatile(...)" instead of just "asm", another way is to use more assembler instructions in one "asm()"-construct like this: asm volatile("asm-instruction1; asm-instruction2; asm-instruction3;"); but to be honest, i often avoid the optimizing flag when using inline-assembler. Michael -- Michael Haertl |
