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hi! i am using a 21065l ez kit lite which has a clock speed of 33 Mhz, which gives an instruction time of about 15 ns. and from the data sheet it says.. Super Harvard Architecture Computer (SHARC) Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle does this mean that i can do I/O fetches every 15 ns (theoretically)? though i tried making a loop which just reads from 0x2000000, and i probed the memory select MS2. i only got pulses with 3.3 MHz frequency. does this mean that i cannot go reading any faster than 3.3MHz? hope someone enlightens me on this.. thanks. |
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speed requirements
Started by ●September 15, 2003
Reply by ●September 16, 20032003-09-16
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On Mon, 15 Sep 2003, lomaguindo wrote: > i am using a 21065l ez kit lite which has a clock speed of 33 > Mhz, which gives an instruction time of about 15 ns. and from the > data sheet it says.. > > Super Harvard Architecture Computer (SHARC) > Four Independent Buses for Dual Data, Instruction, > and I/O Fetch on a Single Cycle > > does this mean that i can do I/O fetches every 15 ns > (theoretically)? though i tried making a loop which just reads from > 0x2000000, and i probed the memory select MS2. i only got pulses with > 3.3 MHz frequency. does this mean that i cannot go reading any faster > than 3.3MHz? hope someone enlightens me on this.. The internal can be done in 1 cycle, but the external is set by the number of wait states in the WAIT register. Theoretically, yes, you can run the external bus at the processor clock speed. But you also have to set up the RDY, internal RDY and number of wait states control correctly. Patience, persistence, truth, Dr. mike |
