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Hi, I am using 21161N, VisualDsp++ 3.0 with SP1 and VDK features. I am using link port 0 and 1 communicate with a Xilinx CPLD. The problem happens when I transmit data from link port 1 to the CPLD. Following the 21161N date sheet, we use CPLD as the receiver and it uses L1ACK to hold link port 1 from transmit the next word until CPLD is ready for it. However, using scope I found Link Port 1 sometimes sporadically transmit a 32-bit word in a middle of a data block without L1ACK been set to high. And that unwanted transmit, do not have 4 L1CLK cycles as for a 32-bit word, it only 2 or 3 L1CLK cycles. I throw out Link port 1 DMA feature, just use interrupt driven core direct write to LBUF1, the problem is still there. Has anyone seen this type of thing before? Any tips? Could it be an anomally of the chip? I read the list, did not see anything that ring a bell. BTW, I am using 1.1 version of the chip. Regards, Lei |
Link port handshake signal problem, help please!
Started by ●October 8, 2003
