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Well, finally got it working. I'd like to note two things: 1. I (erroneously) had the 65L silicione rev. 0.2 on my development board. From previous experience, I know that this causes problems (ie. unusable) in multiple DSP setups with shared SDRAM. 2. On a new development board equipped with rev. 0.3 chips the initialization works if it is done from the DSP core via copy loops. Ie. the host writes a block of data into internal memory of the DSP and the DSP core copies this data from its internal memory into external memory. 3. Also on this rev. 0.3 board, I could _not_ get the DMA based initialization working. I probed further and found that only every fifth value was written correctly by the external port DMA into SDRAM. However, when I set up two DMA after each other, the first writing to all even addresses and the second DMA writing to all odd addresses, the initialization of the SDRAM finally worked OK. I am assuming point 3) is due to a hardware anomaly of the 65L rev. 0.3. Can anyone using their own (dual) 65L boards equipped with SDRAM confirm / counter this SDRAM DMA issue? Regards and thanks to all who answered (and called!), Andor |
SDRAM DMA: Update
Started by ●April 22, 2004
