Qs on Viterbi/Turbo Decoding on Tiger Sharc : Correction

Started by P.B. Srinivas November 17, 2004

Please note I meant state metrics and not states in my earlier email

Hi !

I also posted this Question on the DSP Engineering group, but it
seems more appropriate here..

I am Newbie on TigerSharc Programming, and I am trying to estimate
cycle counts on the TigerSharc for Convolutional/Turbo Decoding.

I have a trellis of just 8 states, and my state metrics registers are
just 16 bits. According to the syntax of the TMAX / ACS instructions,
the inputs are 2 64 bit registers where the state metrics are stored
as s0s1s2s3, s4s5s6s7. However after executing the instruction the
new state metrics get stored into 2 64 bit registers s0s2s4s6
s1s3s5s7. How do I reorder this efficiently ?

It looks like I must transfer these trellis registers to regular
registers and then execute the ALU instruction merge, this seems to
affect my cycle count a lot and seems to be a pretty high price to
pay for reordering..

If any of you have reference to published Code on Turbo/viterbi
decoder on TigerSharc, I would be especially grateful.