ADSP-21369 bus timing issue - async transfers - ACKEN=1

Simply setting the ADSP-21369 AMICTLx register ACKEN bit adds 2
wait-states to reads and 3 wait-states to writes, on top of the
software wait-states.

I would expect no difference if the ACK input is set high, but there
is a difference. Unlike other parts that allow either, neither, the
logical AND or logical OR of sw/hw wait-states, the 2136x has software
wait-states always enabled and hardware wait-states can be optionally
enabled.

Does anybody have experience with this?

I verified the following at bus clock = 166MHz (6ns),
asynchronous memory timing:

WS = 32 cycles (WS bit-field set to zero) - expect
(32+1)*6ns = 198ns per transfer with ACK = HIGH

ACKEN=1, DMA WRITE - 216ns
MS pulses for each DMA transfer

ACKEN=1, DMA READ - 210ns
MS stays low for the duration of the DMA block

ACKEN=0, DMA READ or WRITE - 198ns
MS stays low for the duration of the DMA block

WS = 2 cycles - expect (2+1)*6ns = 18ns per transfer
with ACK = HIGH

ACKEN=1, DMA WRITE - 36ns
MS pulses for each DMA transfer

ACKEN=1, DMA READ - 30ns
MS stays low for the duration of the DMA block

ACKEN=0, DMA READ or WRITE - 18ns
MS stays low for the duration of the DMA block

regards,

Dan Ash Start a New Thread