I'm working on a project involving SPORT1 transfers from a host
processor to 21061
on an EZ-Kit Lite board. Host will send different number of words
depending on what
task Sharc is to perform. Words are to be used by Sharc during
I want to use chained DMA-transfer to put received words direct
into the internal
memory location where it can be read by program. Sharc have no
send words to host. Communication is only from host to Sharc.
Therefore host will
send bits continously until all words are sent. This will se done
at a speed of
about 1 megabit/sec. Word one in transfer is to inform Sharc of
number of succe-
ding words (if any) and where to put it in SRAM. Largest word
transfer are 60 words
and smallest only one word.
I would like to do this in following way:
SPORT1 is initialized to chained DMA-transfer of one word.
PCI bit of (CP) register = 1 to enable SPORT-interrupt.
When word is received and moved into SRAM interrupt occurs.
Interrupt service routine write new chain pointer for SPORT.
This chain pointer is different depending on first word.
When done core returns to normal program flow (circular buffer).
Next block is received in SPORT and moved to proper SRAM-location.
PCI bit of (CP) register = 0 to disable interrupts between blocks.
Possibly procedure is repeated until all blocks are received.
In last (CP) PCI bit = 1 to enable interrupt when all words are
What I can't figure out is how Sharc treat the continous flow of
bits on SPORT.
* Will there be lost bits when changing chain-pointer?
* Will the few bits loaded into RX-buffer before new chain-pointer
end up in old adress? (First interrupt routine is only 4-5
since Sharc run at 40 MHz only one or two bits are sent between
and second chain-pointer is loaded).Possibly other interrupts being
will add to this delay.
* Will SPORT RX-buffer stop receiving words until interrupt is
My interpretation of Sharc users manual 10.3.4.1 last part is
that no bits will
be lost if more than 7 bits/word is sent at full speed. (I'm not
even close to
this bit rate). I also get a hunch when reading manual that bits
are loaded to
RX-buffer if SPORT is enabled even if Sharc do other things such
as loading new
TCB-block or service interrupts, but I have not managed to find a
stating this clearly.
Possibly host can do some nop's between blocks to give Sharc time
new TCB but SPORT transfer will be one of two "bottle-necks" of
and I don't want to add to this with nop's if not needed.
If anybody got a clue of Sharc's SPORT behavior please let me know Richard