help needed

Problems with project in technical note EE-268 (Programming
Asynchronous Sample Rate Converters on ADSP-2136x) on ADSP-21369.

I started project “SRC SPORT0 to SPORT1” on ADSP-21369
(dspblok™ 21369zx). I have changed code for porting on ADSP21369
only by including files. But I have got output values in the negative
and added ‘DTYPE1 bit’ in Sport1Init (). There are noises
in output signal.

I have no idea about it. Where is the mistake? Code listing below:

View code in main():

/Function Definitions
--------------------------

//----------------------------------\
-------------

//Initialize SRC0

void SRC0Init()

{

*pSRCCTL0 = SRC0_SMODEIN0 | SRC0_SMODEOUT0 | SRC0_ENABLE ;

}

//-------------------

//-------------------

//Initialize SPORT0

void Sport0Init()

{

*pDIV0 = 0x0018000e;

*pSPCTL0 |= SPEN_A | SLEN24 | MSTR | OPMODE |
SPTRAN;//SPORT0 configuration:

//Internal clock and word select

//I2S mode

//Transmitter

//Word length 24

}

//-------------------

//-------------------

//Initialize SPORT1

void Sport1Init()

{

*pDIV1 = 0x0018000e;

*pSPCTL1 |= SPEN_A | MSTR | SLEN24 | OPMODE | DTYPE1;
//SPORT1 configuration:

//Internal clock and word select

//I2S mode

//Receiver

//Word length 24

}

View code in SPORT_0_1 and SRC0.c

// This function will setup the SRU Registers

void InitSRU()

{

// Enable pull-up resistors on unused DAI pins

* (volatile int *)DAI_PIN_PULLUP = 0xfffff;

//Generating Code for connecting : SPORT0_CLK to SRC0_CLK_IP

SRU (SPORT0_CLK_O, SRC0_CLK_IP_I);

//Generating Code for connecting : SPORT0_FS to SRC0_FS_IP

SRU (SPORT0_FS_O, SRC0_FS_IP_I);

//Generating Code for connecting : SPORT0_DA to SRC0_DAT_IP

SRU (SPORT0_DA_O, SRC0_DAT_IP_I);

//Generating Code for connecting : SPORT1_CLK to SRC0_CLK_OP

SRU (SPORT1_CLK_O, SRC0_CLK_OP_I);

//Generating Code for connecting : SPORT1_FS to SRC0_FS_OP

SRU (SPORT1_FS_O, SRC0_FS_OP_I);

//Generating Code for connecting : SRC0_DAT_OP to SPORT1_DA

SRU (SRC0_DAT_OP_O, SPORT1_DA_I);

}

Excuse me for my bad English. Start a New Thread

Your English is way better than my Russian!!
On Wed, 28 Sep 2011, polcoolov wrote:

> Problems with project in technical note EE-268 (Programming
> Asynchronous Sample Rate Converters on ADSP-2136x) on ADSP-21369.
>
> I started project “SRC SPORT0 to SPORT1” on ADSP-21369
> (dspblok™ 21369zx). I have changed code for porting on ADSP21369
> only by including files. But I have got output values in the negative
> and added ‘DTYPE1 bit’ in Sport1Init (). There are noises
> in output signal.

When you say "noise" do you mean there no recognizable signal at all? Or
is the base signal there with some randomness on top of it? If the
former, then check the pDIVx values, maybe there is a difference in how
the devices work.

Also, what is the amplitude of the noise compared to the signal? How is
the hardware different between the two projects? There are a lot of
possible places for things to go wrong, it might not just be code.

Patience, persistence, truth,
Dr. mike Start a New Thread

Hi, Mike!
Thanks for your answer. I have given not sufficient information about my project. Excuse me, I am “newcomer”.

Yes, base signal is there with some randomness on top of it. Look plot output signal in attached file for case FsOUT = FsIN. Amplitude of the noise is 1 – 10 bit. Output signal is triangle wave, but the data consisting it is “jumping” regarding “right” data.

Hardware description:
- ADSP-21369 (dspblok™ 21369zx);
- Emulator USB-ICE.
- Core Clock 398,131 MHz

Code determinates work of Serial ports:

- CLKDIV = 0x0E;
- Word length = 0x18;
- FSDIV = 0x18;

1. Calculation for SCLK Serial Port:
SCLK = PCLK/4(CLKDIV +1) = 3,31 MHz.(page 7-9 of ADSP-2137x SHARC® Processor Hardware Reference)
SCLK is satisfactory for SCLK 2. Calculation for Sample Rate Serial Port:
Sample rate = SCLK/ FSDIV = 138 kHz. It is satisfactory for Sample rate < 192 kHz (page 9-2 of ADSP-2137x SHARC® Processor Hardware Reference).

Formulas and conditions are equal for ADSP-21369 and ADSP-21364. Start a New Thread