ADC time issue

Started by Song Lin March 24, 2009
I have a few questions about ADC time.

1. In the ADC reference guide (SPRU060D), it shows on page 1-7 that, in simultaneous mode, 4 ADC clock periods are required before the result data is available for C1. Since the ADC clock is 25MHz at most, does that mean the highest sampling rate is 25/4 = 6.25MHz?

2. Is it better to use bigger SH width? The bigger it is, the slower the smapling rate?

3. How to calculate the total time needed in simultaneous mode to sample 3 channels on each side, i.e., 3 on A and 3 on B.

You must care about acquisition period, Acqps. Refer to ADC Calibration.pdf from page 8 to 13 where you find how to calculate total time. If you choose bigger SH width you have the slower sampling rate but your ADC is significantly accurate, that is very essential.