|
what could be the maximum timer frequency in clock mode with 150MHz
VC33?
Saqib Ali
|
Max timer frequency!
Started by ●February 14, 2004
Reply by ●February 16, 20042004-02-16
|
Hello Saqib Fmax would be 37.5Mhz. The four clock outputs TCLK0, TCLK1, CLKX and CLKR have output frequencies that are also dependent on the timer mode. Fclk = Fh/(2*Tprd) Pulse mode , Period of 0 not allowed Fclk = Fh/(4*Tprd) Square mode, Period of 0 allowed but output is Fh/2 As you can see both modes will generate the same Maximum frequency, but the pulse mode will give you 2x the frequency resolution. BTW, the pulse width is 1/Fh. Hope this helps, Keith Larson ------ At 01:56 PM 2/14/04 -0800, you wrote: what could be the maximum timer frequency in clock mode with 150MHz VC33? Saqib Ali +--------------------------+ | Keith Larson | | Member Group Technical Staff | | Texas Instruments Incorporated | | | | 281-274-3288 | | | | www.micro.ti.com/~klarson (TI internal web only) | |--------------------------+ | TMS320C3x/C4x/VC33 Applications | | | | TMS320VC33 | | The lowest cost and lowest power 500 w/Mflop | | floating point DSP on the planet! | | | | Web: focus.ti.com/docs/toolsw/folders/print/tmdsdsk33.html | | Code: www-s.ti.com/sc/psheets/sprc147/sprc147.zip | +--------------------------+ |
Reply by ●February 19, 20042004-02-19
|
Hello Saqib I dont wish to directly answer this since I think it would be best if you can figure this out from the TMS320C3x Device Users Guide, or at least find the provided DSK examples (scan for T0_ctrl). Here you will find that there are only three registers, and two of them are the period and count values almost making them 'dont cares'. Basically you need to start with the bits in the Timer Global Global Control Register (most DSK examples use the lable T0_ctrl). Bit-banging values into the timer using the debugger is another way to familiarize, but it wont tell you how to write code. Basically you would open a memory window showing the timer registers and bit-bang poke values in with the debugger. You may notice some curious things like when you write a value to T0_prd, T0_cnt sometimes goes 'over'. The solution is to afterwards write a value of zero to T0_cnt or restart the timer by setting the GO bit. Or, as I said copy and paste some code from the provided C or ASM examples. Hint: scan for 'T0_ctrl' Best regards, Keith Larson ================================================== At 12:00 AM 2/19/04 -0800, you wrote: Dear Larson, Can you give me the code for initializing the timer at this much rate (37.5MHz) . ? Regards Saqib Ali ================================================== "Keith E. Larson" <> wrote: Hello Saqib Fmax would be 37.5Mhz. The four clock outputs TCLK0, TCLK1, CLKX and CLKR have output frequencies that are also dependent on the timer mode. Fclk = Fh/(2*Tprd) Pulse mode , Period of 0 not allowed Fclk = Fh/(4*Tprd) Square mode, Period of 0 allowed but output is Fh/2 As you can see both modes will generate the same Maximum frequency, but the pulse mode will give you 2x the frequency resolution. BTW, the pulse width is 1/Fh. Hope this helps, Keith Larson ------ At 01:56 PM 2/14/04 -0800, you wrote: what could be the maximum timer frequency in clock mode with 150MHz VC33? Saqib Ali +--------------------------+ | Keith Larson | | Member Group Technical Staff | | Texas Instruments Incorporated | | | | 281-274-3288 | | | | www.micro.ti.com/~klarson (TI internal web only) | |--------------------------+ | TMS320C3x/C4x/VC33 Applications | | | | TMS320VC33 | | The lowest cost and lowest power 500 w/Mflop | | floating point DSP on the planet! | | | | Web: focus.ti.com/docs/toolsw/folders/print/tmdsdsk33.html | | Code: www-s.ti.com/sc/psheets/sprc147/sprc147.zip | +--------------------------+ |
