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Good day. Say DMA channel 2 is configured to do a block transfer of one frame with 256 elements. When data is received via MsBSP1 (DRR11), REVT will caused a DMA channel 2 interrupt. Now, my understanding till now is that DMA will collect 256 data and send all 256 data in a block transfer to destination memory location. My question : Where did DMA store the data collected before the block transfer? Is there a buffer within DMA controller? If yes, how much data can it store? Thanks & regards, Doreen |
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DMA
Started by ●December 4, 2000
Reply by ●December 5, 20002000-12-05
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Hi Doreen, Each sync event (REVT) causes the DMA controller to transfer 1 word from source address (DRR) to the destination address(some memory). Depending on the size of the destination buffer & programming of the interrupts, an interrupt occurs when half buffer or full buffer is filled with data. The DMA controller does not wait for the entire block of 256 words to arrive & hence doesn't need an intermediate storage. Reference : TMS320C54X DSP Enhanced Peripherals (Reference Set Vol 5) With Regards, SATHEESH.S On Mon, 4 Dec 2000, Doreen Yeo Lee Guek wrote: > Good day. > > Say DMA channel 2 is configured to do a block transfer of one frame with 256 > elements. When data is received via MsBSP1 (DRR11), REVT will caused a DMA > channel 2 interrupt. Now, my understanding till now is that DMA will collect > 256 data and send all 256 data in a block transfer to destination memory > location. > > My question : Where did DMA store the data collected before the block > transfer? Is there a buffer within DMA controller? If yes, how much data can > it store? > > Thanks & regards, > Doreen > To Join: Send an email to > > To Post: Send an email to > > To Leave: Send an email to > > Archives: http://www.egroups.com/group/c54x > > Other Groups: http://www.dsprelated.com > |
