Hi ,
I am working with TMS320C5509A emif and facing a similar problem.
When I write address for CE spaces no Chip select is generated. By default CE
signal for CE space CE1 is generated for any address.
I am writing address as shown below.
*(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
Also if I write statement where should i be able to see the data in Memory
window of CCS 3.3V code composer studio.
Regards,
Onkar
Problem with 5509A address space and CE generation
Started by ●May 13, 2008
Reply by ●May 13, 20082008-05-13
Onkar-
> I am working with TMS320C5509A emif and facing a similar problem.
Which board?
> When I write address for CE spaces no Chip select is generated.
How do you know it's not generated? How do you measure the signal?
> By default CE signal for CE space CE1 is generated for any address.
There are separate CEn signals on the chip, not just one "CE signal". Look up pins
C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> I am writing address as shown below.
> *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
>
> Also if I write statement where should i be able to see the data in
> Memory window of CCS 3.3V code composer studio.
First you have to say which board you are using. Some boards may have memory chips
connected to CE2, some may not. Also it's possible the board was designed so that
HPI is enabled, in which case some CE2-related pins are used for HPI.
-Jeff
> I am working with TMS320C5509A emif and facing a similar problem.
Which board?
> When I write address for CE spaces no Chip select is generated.
How do you know it's not generated? How do you measure the signal?
> By default CE signal for CE space CE1 is generated for any address.
There are separate CEn signals on the chip, not just one "CE signal". Look up pins
C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> I am writing address as shown below.
> *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
>
> Also if I write statement where should i be able to see the data in
> Memory window of CCS 3.3V code composer studio.
First you have to say which board you are using. Some boards may have memory chips
connected to CE2, some may not. Also it's possible the board was designed so that
HPI is enabled, in which case some CE2-related pins are used for HPI.
-Jeff
Reply by ●May 14, 20082008-05-14
Dear Jeff,
thanks for the reply.
I am working on a customized board where CE1 is connected to FLASH, CE2 is connected to SRAM and CE3 is connected to FPGA. I am using it in FULL EMIF mode.
On the board, using CRO I am verifying whether CE1,2,3 is getting generated or not.
Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am getting CE1,2,3 for different addresses, but not for the code I am writing for memory write which is as...
long *regdata_SRAM;
regdata_SRAM = 0x00400000 ;// CE2 space in word mode
*regdata_SRAM = i;// i is any data
And with change in address like 0x00200000 , 0x00400000 , 0x00600000 I am expecting different CE to get generated.
Waiting for reply.
Regards,
Onkar Patki,
Design Engineer.
----------------------------
Mechatronics Test Equipment (I) Pvt.Ltd.
B, Mayur complex, Opp. Bhelke nagar,
Kothrud, Pune 411 038.
Tel.: 91 20 25386926,27,28,29
Fax:: 91 20 25386930
Mob: 919881730876
Email: m...@vsnl.net
URL: www.mte-india.com
----- Original Message -----
From: Jeff Brower
To: Patki Onkar
Cc: c...
Sent: Tuesday, May 13, 2008 7:51 PM
Subject: Re: [c55x] Problem with 5509A address space and CE generation
Onkar-
> I am working with TMS320C5509A emif and facing a similar problem.
Which board?
> When I write address for CE spaces no Chip select is generated.
How do you know it's not generated? How do you measure the signal?
> By default CE signal for CE space CE1 is generated for any address.
There are separate CEn signals on the chip, not just one "CE signal". Look up pins
C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> I am writing address as shown below.
> *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
>
> Also if I write statement where should i be able to see the data in
> Memory window of CCS 3.3V code composer studio.
First you have to say which board you are using. Some boards may have memory chips
connected to CE2, some may not. Also it's possible the board was designed so that
HPI is enabled, in which case some CE2-related pins are used for HPI.
-Jeff
thanks for the reply.
I am working on a customized board where CE1 is connected to FLASH, CE2 is connected to SRAM and CE3 is connected to FPGA. I am using it in FULL EMIF mode.
On the board, using CRO I am verifying whether CE1,2,3 is getting generated or not.
Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am getting CE1,2,3 for different addresses, but not for the code I am writing for memory write which is as...
long *regdata_SRAM;
regdata_SRAM = 0x00400000 ;// CE2 space in word mode
*regdata_SRAM = i;// i is any data
And with change in address like 0x00200000 , 0x00400000 , 0x00600000 I am expecting different CE to get generated.
Waiting for reply.
Regards,
Onkar Patki,
Design Engineer.
----------------------------
Mechatronics Test Equipment (I) Pvt.Ltd.
B, Mayur complex, Opp. Bhelke nagar,
Kothrud, Pune 411 038.
Tel.: 91 20 25386926,27,28,29
Fax:: 91 20 25386930
Mob: 919881730876
Email: m...@vsnl.net
URL: www.mte-india.com
----- Original Message -----
From: Jeff Brower
To: Patki Onkar
Cc: c...
Sent: Tuesday, May 13, 2008 7:51 PM
Subject: Re: [c55x] Problem with 5509A address space and CE generation
Onkar-
> I am working with TMS320C5509A emif and facing a similar problem.
Which board?
> When I write address for CE spaces no Chip select is generated.
How do you know it's not generated? How do you measure the signal?
> By default CE signal for CE space CE1 is generated for any address.
There are separate CEn signals on the chip, not just one "CE signal". Look up pins
C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> I am writing address as shown below.
> *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
>
> Also if I write statement where should i be able to see the data in
> Memory window of CCS 3.3V code composer studio.
First you have to say which board you are using. Some boards may have memory chips
connected to CE2, some may not. Also it's possible the board was designed so that
HPI is enabled, in which case some CE2-related pins are used for HPI.
-Jeff
Reply by ●May 15, 20082008-05-15
Onkar-
> thanks for the reply.
> I am working on a customized board where CE1 is connected to FLASH,
> CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> it in FULL EMIF mode.
Ok, thanks for explaining.
> On the board, using CRO I am verifying whether CE1,2,3 is getting
> generated or not.
Ok.
> Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> getting CE1,2,3 for different addresses, but not for the code I am
> writing for memory write which is as...
>
> long *regdata_SRAM;
> regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> *regdata_SRAM = i;// i is any data
>
> And with change in address like 0x00200000 , 0x00400000 ,
> 0x00600000 I am expecting different CE to get generated.
Well it could be a number of things. One thing you might try is code like:
*(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
as that tells the compiler "make this memory write even though the contents are never
accessed (read)". Otherwise the compiler may ignore the write and not generate the
actual code.
Other possibilities include:
-your code not enabling EMIF32 bus access
by writing to IO space addr 0x6c00
-your code not setting correct EMIF registers
(EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
-you not capturing single CE2 pulses correctly
on the dig scope (unlike multiple accesses
or burst of accesses during code download,
which are easier to see)
-Jeff
> ----------------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Patki Onkar
> Cc: c...
> Sent: Tuesday, May 13, 2008 7:51 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > I am working with TMS320C5509A emif and facing a similar problem.
>
> Which board?
>
> > When I write address for CE spaces no Chip select is generated.
>
> How do you know it's not generated? How do you measure the signal?
>
> > By default CE signal for CE space CE1 is generated for any address.
>
> There are separate CEn signals on the chip, not just one "CE signal". Look up pins
> C4-C7 in the 5509A data sheet. Only one is generated at any one time.
>
> > I am writing address as shown below.
> > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
> >
> > Also if I write statement where should i be able to see the data in
> > Memory window of CCS 3.3V code composer studio.
>
> First you have to say which board you are using. Some boards may have memory chips
> connected to CE2, some may not. Also it's possible the board was designed so that
> HPI is enabled, in which case some CE2-related pins are used for HPI.
>
> -Jeff
> thanks for the reply.
> I am working on a customized board where CE1 is connected to FLASH,
> CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> it in FULL EMIF mode.
Ok, thanks for explaining.
> On the board, using CRO I am verifying whether CE1,2,3 is getting
> generated or not.
Ok.
> Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> getting CE1,2,3 for different addresses, but not for the code I am
> writing for memory write which is as...
>
> long *regdata_SRAM;
> regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> *regdata_SRAM = i;// i is any data
>
> And with change in address like 0x00200000 , 0x00400000 ,
> 0x00600000 I am expecting different CE to get generated.
Well it could be a number of things. One thing you might try is code like:
*(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
as that tells the compiler "make this memory write even though the contents are never
accessed (read)". Otherwise the compiler may ignore the write and not generate the
actual code.
Other possibilities include:
-your code not enabling EMIF32 bus access
by writing to IO space addr 0x6c00
-your code not setting correct EMIF registers
(EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
-you not capturing single CE2 pulses correctly
on the dig scope (unlike multiple accesses
or burst of accesses during code download,
which are easier to see)
-Jeff
> ----------------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Patki Onkar
> Cc: c...
> Sent: Tuesday, May 13, 2008 7:51 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > I am working with TMS320C5509A emif and facing a similar problem.
>
> Which board?
>
> > When I write address for CE spaces no Chip select is generated.
>
> How do you know it's not generated? How do you measure the signal?
>
> > By default CE signal for CE space CE1 is generated for any address.
>
> There are separate CEn signals on the chip, not just one "CE signal". Look up pins
> C4-C7 in the 5509A data sheet. Only one is generated at any one time.
>
> > I am writing address as shown below.
> > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
> >
> > Also if I write statement where should i be able to see the data in
> > Memory window of CCS 3.3V code composer studio.
>
> First you have to say which board you are using. Some boards may have memory chips
> connected to CE2, some may not. Also it's possible the board was designed so that
> HPI is enabled, in which case some CE2-related pins are used for HPI.
>
> -Jeff
Reply by ●May 15, 20082008-05-15
Hi Jeff,
Thanks for reply.
I am using 16 bit EMIF bus and I could observe (EMIF_GCTL1,EMIF_CE21 etc ) registers are getting set properly through Emulator.
Even EBSR @ address 0x6C00 is getting set correctly for full emif mode.
I could not get what do you mean by
"-your code not enabling EMIF32 bus access by writing to IO space addr 0x6c00"
Regards,
Onkar Patki,
Design Engineer.
----------------------------
Mechatronics Test Equipment (I) Pvt.Ltd.
B, Mayur complex, Opp. Bhelke nagar,
Kothrud, Pune 411 038.
Tel.: 91 20 25386926,27,28,29
Fax:: 91 20 25386930
Mob: 919881730876
Email: m...@vsnl.net
URL: www.mte-india.com
----- Original Message -----
From: Jeff Brower
To: Onkar Patki
Cc: c...
Sent: Thursday, May 15, 2008 12:15 PM
Subject: Re: [c55x] Problem with 5509A address space and CE generation
Onkar-
> thanks for the reply.
> I am working on a customized board where CE1 is connected to FLASH,
> CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> it in FULL EMIF mode.
Ok, thanks for explaining.
> On the board, using CRO I am verifying whether CE1,2,3 is getting
> generated or not.
Ok.
> Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> getting CE1,2,3 for different addresses, but not for the code I am
> writing for memory write which is as...
>
> long *regdata_SRAM;
> regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> *regdata_SRAM = i;// i is any data
>
> And with change in address like 0x00200000 , 0x00400000 ,
> 0x00600000 I am expecting different CE to get generated.
Well it could be a number of things. One thing you might try is code like:
*(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
as that tells the compiler "make this memory write even though the contents are never
accessed (read)". Otherwise the compiler may ignore the write and not generate the
actual code.
Other possibilities include:
-your code not enabling EMIF32 bus access
by writing to IO space addr 0x6c00
-your code not setting correct EMIF registers
(EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
-you not capturing single CE2 pulses correctly
on the dig scope (unlike multiple accesses
or burst of accesses during code download,
which are easier to see)
-Jeff
> ----------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Patki Onkar
> Cc: c...
> Sent: Tuesday, May 13, 2008 7:51 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > I am working with TMS320C5509A emif and facing a similar problem.
>
> Which board?
>
> > When I write address for CE spaces no Chip select is generated.
>
> How do you know it's not generated? How do you measure the signal?
>
> > By default CE signal for CE space CE1 is generated for any address.
>
> There are separate CEn signals on the chip, not just one "CE signal". Look up pins
> C4-C7 in the 5509A data sheet. Only one is generated at any one time.
>
> > I am writing address as shown below.
> > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
> >
> > Also if I write statement where should i be able to see the data in
> > Memory window of CCS 3.3V code composer studio.
>
> First you have to say which board you are using. Some boards may have memory chips
> connected to CE2, some may not. Also it's possible the board was designed so that
> HPI is enabled, in which case some CE2-related pins are used for HPI.
>
> -Jeff
Thanks for reply.
I am using 16 bit EMIF bus and I could observe (EMIF_GCTL1,EMIF_CE21 etc ) registers are getting set properly through Emulator.
Even EBSR @ address 0x6C00 is getting set correctly for full emif mode.
I could not get what do you mean by
"-your code not enabling EMIF32 bus access by writing to IO space addr 0x6c00"
Regards,
Onkar Patki,
Design Engineer.
----------------------------
Mechatronics Test Equipment (I) Pvt.Ltd.
B, Mayur complex, Opp. Bhelke nagar,
Kothrud, Pune 411 038.
Tel.: 91 20 25386926,27,28,29
Fax:: 91 20 25386930
Mob: 919881730876
Email: m...@vsnl.net
URL: www.mte-india.com
----- Original Message -----
From: Jeff Brower
To: Onkar Patki
Cc: c...
Sent: Thursday, May 15, 2008 12:15 PM
Subject: Re: [c55x] Problem with 5509A address space and CE generation
Onkar-
> thanks for the reply.
> I am working on a customized board where CE1 is connected to FLASH,
> CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> it in FULL EMIF mode.
Ok, thanks for explaining.
> On the board, using CRO I am verifying whether CE1,2,3 is getting
> generated or not.
Ok.
> Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> getting CE1,2,3 for different addresses, but not for the code I am
> writing for memory write which is as...
>
> long *regdata_SRAM;
> regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> *regdata_SRAM = i;// i is any data
>
> And with change in address like 0x00200000 , 0x00400000 ,
> 0x00600000 I am expecting different CE to get generated.
Well it could be a number of things. One thing you might try is code like:
*(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
as that tells the compiler "make this memory write even though the contents are never
accessed (read)". Otherwise the compiler may ignore the write and not generate the
actual code.
Other possibilities include:
-your code not enabling EMIF32 bus access
by writing to IO space addr 0x6c00
-your code not setting correct EMIF registers
(EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
-you not capturing single CE2 pulses correctly
on the dig scope (unlike multiple accesses
or burst of accesses during code download,
which are easier to see)
-Jeff
> ----------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Patki Onkar
> Cc: c...
> Sent: Tuesday, May 13, 2008 7:51 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > I am working with TMS320C5509A emif and facing a similar problem.
>
> Which board?
>
> > When I write address for CE spaces no Chip select is generated.
>
> How do you know it's not generated? How do you measure the signal?
>
> > By default CE signal for CE space CE1 is generated for any address.
>
> There are separate CEn signals on the chip, not just one "CE signal". Look up pins
> C4-C7 in the 5509A data sheet. Only one is generated at any one time.
>
> > I am writing address as shown below.
> > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
> >
> > Also if I write statement where should i be able to see the data in
> > Memory window of CCS 3.3V code composer studio.
>
> First you have to say which board you are using. Some boards may have memory chips
> connected to CE2, some may not. Also it's possible the board was designed so that
> HPI is enabled, in which case some CE2-related pins are used for HPI.
>
> -Jeff
Reply by ●May 15, 20082008-05-15
Onkar-
> Thanks for reply.
>
> I am using 16 bit EMIF bus and I could observe (EMIF_GCTL1,EMIF_CE21 etc )
> registers are getting set properly through Emulator.
>
> Even EBSR @ address 0x6C00 is getting set correctly for full emif mode.
>
> I could not get what do you mean by
> "-your code not enabling EMIF32 bus access by writing to IO space addr
> 0x6c00"
When you write to EBSR (0x6c00), are you doing an I/O port write? The EBSR register
is in onchip mem, but located in I/O space, so you have to use a C code line similar
to:
*((ioport int*)0x6C00) = 1; // enable EMIF32
-Jeff
> ----------------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Onkar Patki
> Cc: c...
> Sent: Thursday, May 15, 2008 12:15 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > thanks for the reply.
> > I am working on a customized board where CE1 is connected to FLASH,
> > CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> > it in FULL EMIF mode.
>
> Ok, thanks for explaining.
>
> > On the board, using CRO I am verifying whether CE1,2,3 is getting
> > generated or not.
>
> Ok.
>
> > Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> > getting CE1,2,3 for different addresses, but not for the code I am
> > writing for memory write which is as...
> >
> > long *regdata_SRAM;
> > regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> > *regdata_SRAM = i;// i is any data
> >
> > And with change in address like 0x00200000 , 0x00400000 ,
> > 0x00600000 I am expecting different CE to get generated.
>
> Well it could be a number of things. One thing you might try is code like:
>
> *(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
>
> as that tells the compiler "make this memory write even though the contents are never
> accessed (read)". Otherwise the compiler may ignore the write and not generate the
> actual code.
>
> Other possibilities include:
>
> -your code not enabling EMIF32 bus access
> by writing to IO space addr 0x6c00
>
> -your code not setting correct EMIF registers
> (EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
>
> -you not capturing single CE2 pulses correctly
> on the dig scope (unlike multiple accesses
> or burst of accesses during code download,
> which are easier to see)
>
> -Jeff
>
> > ----------------------
> > Mechatronics Test Equipment (I) Pvt.Ltd.
> > B, Mayur complex, Opp. Bhelke nagar,
> > Kothrud, Pune 411 038.
> > Tel.: 91 20 25386926,27,28,29
> > Fax:: 91 20 25386930
> > Mob: 919881730876
> > Email: m...@vsnl.net
> > URL: www.mte-india.com
> >
> > ----- Original Message -----
> > From: Jeff Brower
> > To: Patki Onkar
> > Cc: c...
> > Sent: Tuesday, May 13, 2008 7:51 PM
> > Subject: Re: [c55x] Problem with 5509A address space and CE generation
> >
> > Onkar-
> >
> > > I am working with TMS320C5509A emif and facing a similar problem.
> >
> > Which board?
> >
> > > When I write address for CE spaces no Chip select is generated.
> >
> > How do you know it's not generated? How do you measure the signal?
> >
> > > By default CE signal for CE space CE1 is generated for any address.
> >
> > There are separate CEn signals on the chip, not just one "CE signal". Look up pins
> > C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> >
> > > I am writing address as shown below.
> > > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
> > >
> > > Also if I write statement where should i be able to see the data in
> > > Memory window of CCS 3.3V code composer studio.
> >
> > First you have to say which board you are using. Some boards may have memory chips
> > connected to CE2, some may not. Also it's possible the board was designed so that
> > HPI is enabled, in which case some CE2-related pins are used for HPI.
> >
> > -Jeff
> Thanks for reply.
>
> I am using 16 bit EMIF bus and I could observe (EMIF_GCTL1,EMIF_CE21 etc )
> registers are getting set properly through Emulator.
>
> Even EBSR @ address 0x6C00 is getting set correctly for full emif mode.
>
> I could not get what do you mean by
> "-your code not enabling EMIF32 bus access by writing to IO space addr
> 0x6c00"
When you write to EBSR (0x6c00), are you doing an I/O port write? The EBSR register
is in onchip mem, but located in I/O space, so you have to use a C code line similar
to:
*((ioport int*)0x6C00) = 1; // enable EMIF32
-Jeff
> ----------------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Onkar Patki
> Cc: c...
> Sent: Thursday, May 15, 2008 12:15 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > thanks for the reply.
> > I am working on a customized board where CE1 is connected to FLASH,
> > CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> > it in FULL EMIF mode.
>
> Ok, thanks for explaining.
>
> > On the board, using CRO I am verifying whether CE1,2,3 is getting
> > generated or not.
>
> Ok.
>
> > Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> > getting CE1,2,3 for different addresses, but not for the code I am
> > writing for memory write which is as...
> >
> > long *regdata_SRAM;
> > regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> > *regdata_SRAM = i;// i is any data
> >
> > And with change in address like 0x00200000 , 0x00400000 ,
> > 0x00600000 I am expecting different CE to get generated.
>
> Well it could be a number of things. One thing you might try is code like:
>
> *(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
>
> as that tells the compiler "make this memory write even though the contents are never
> accessed (read)". Otherwise the compiler may ignore the write and not generate the
> actual code.
>
> Other possibilities include:
>
> -your code not enabling EMIF32 bus access
> by writing to IO space addr 0x6c00
>
> -your code not setting correct EMIF registers
> (EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
>
> -you not capturing single CE2 pulses correctly
> on the dig scope (unlike multiple accesses
> or burst of accesses during code download,
> which are easier to see)
>
> -Jeff
>
> > ----------------------
> > Mechatronics Test Equipment (I) Pvt.Ltd.
> > B, Mayur complex, Opp. Bhelke nagar,
> > Kothrud, Pune 411 038.
> > Tel.: 91 20 25386926,27,28,29
> > Fax:: 91 20 25386930
> > Mob: 919881730876
> > Email: m...@vsnl.net
> > URL: www.mte-india.com
> >
> > ----- Original Message -----
> > From: Jeff Brower
> > To: Patki Onkar
> > Cc: c...
> > Sent: Tuesday, May 13, 2008 7:51 PM
> > Subject: Re: [c55x] Problem with 5509A address space and CE generation
> >
> > Onkar-
> >
> > > I am working with TMS320C5509A emif and facing a similar problem.
> >
> > Which board?
> >
> > > When I write address for CE spaces no Chip select is generated.
> >
> > How do you know it's not generated? How do you measure the signal?
> >
> > > By default CE signal for CE space CE1 is generated for any address.
> >
> > There are separate CEn signals on the chip, not just one "CE signal". Look up pins
> > C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> >
> > > I am writing address as shown below.
> > > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
> > >
> > > Also if I write statement where should i be able to see the data in
> > > Memory window of CCS 3.3V code composer studio.
> >
> > First you have to say which board you are using. Some boards may have memory chips
> > connected to CE2, some may not. Also it's possible the board was designed so that
> > HPI is enabled, in which case some CE2-related pins are used for HPI.
> >
> > -Jeff
Reply by ●May 16, 20082008-05-16
Hi Jeff,
I tried the way suggested by you to write EBSR register...
*((ioport int*)0x6C00 = 0x0001;
So, according to the description of EBSR register, atleast CLKOUT of DSP should get disabled but still at the CLKOUT pin/test point of DSP I am able to observe the 30MHz clock.
So I am feeling that the EBSR register is not getting set.
Regards,
Onkar Patki,
Design Engineer.
----------------------------
Mechatronics Test Equipment (I) Pvt.Ltd.
B, Mayur complex, Opp. Bhelke nagar,
Kothrud, Pune 411 038.
Tel.: 91 20 25386926,27,28,29
Fax:: 91 20 25386930
Mob: 919881730876
Email: m...@vsnl.net
URL: www.mte-india.com
----- Original Message -----
From: Jeff Brower
To: Onkar Patki
Cc: c...
Sent: Thursday, May 15, 2008 10:24 PM
Subject: Re: [c55x] Problem with 5509A address space and CE generation
Onkar-
> Thanks for reply.
>
> I am using 16 bit EMIF bus and I could observe (EMIF_GCTL1,EMIF_CE21 etc )
> registers are getting set properly through Emulator.
>
> Even EBSR @ address 0x6C00 is getting set correctly for full emif mode.
>
> I could not get what do you mean by
> "-your code not enabling EMIF32 bus access by writing to IO space addr
> 0x6c00"
When you write to EBSR (0x6c00), are you doing an I/O port write? The EBSR register
is in onchip mem, but located in I/O space, so you have to use a C code line similar
to:
*((ioport int*)0x6C00) = 1; // enable EMIF32
-Jeff
> ----------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Onkar Patki
> Cc: c...
> Sent: Thursday, May 15, 2008 12:15 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > thanks for the reply.
> > I am working on a customized board where CE1 is connected to FLASH,
> > CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> > it in FULL EMIF mode.
>
> Ok, thanks for explaining.
>
> > On the board, using CRO I am verifying whether CE1,2,3 is getting
> > generated or not.
>
> Ok.
>
> > Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> > getting CE1,2,3 for different addresses, but not for the code I am
> > writing for memory write which is as...
> >
> > long *regdata_SRAM;
> > regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> > *regdata_SRAM = i;// i is any data
> >
> > And with change in address like 0x00200000 , 0x00400000 ,
> > 0x00600000 I am expecting different CE to get generated.
>
> Well it could be a number of things. One thing you might try is code like:
>
> *(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
>
> as that tells the compiler "make this memory write even though the contents are never
> accessed (read)". Otherwise the compiler may ignore the write and not generate the
> actual code.
>
> Other possibilities include:
>
> -your code not enabling EMIF32 bus access
> by writing to IO space addr 0x6c00
>
> -your code not setting correct EMIF registers
> (EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
>
> -you not capturing single CE2 pulses correctly
> on the dig scope (unlike multiple accesses
> or burst of accesses during code download,
> which are easier to see)
>
> -Jeff
>
> > ----------------------
> > Mechatronics Test Equipment (I) Pvt.Ltd.
> > B, Mayur complex, Opp. Bhelke nagar,
> > Kothrud, Pune 411 038.
> > Tel.: 91 20 25386926,27,28,29
> > Fax:: 91 20 25386930
> > Mob: 919881730876
> > Email: m...@vsnl.net
> > URL: www.mte-india.com
> >
> > ----- Original Message -----
> > From: Jeff Brower
> > To: Patki Onkar
> > Cc: c...
> > Sent: Tuesday, May 13, 2008 7:51 PM
> > Subject: Re: [c55x] Problem with 5509A address space and CE generation
> >
> > Onkar-
> >
> > > I am working with TMS320C5509A emif and facing a similar problem.
> >
> > Which board?
> >
> > > When I write address for CE spaces no Chip select is generated.
> >
> > How do you know it's not generated? How do you measure the signal?
> >
> > > By default CE signal for CE space CE1 is generated for any address.
> >
> > There are separate CEn signals on the chip, not just one "CE signal". Look up pins
> > C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> >
> > > I am writing address as shown below.
> > > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
> > >
> > > Also if I write statement where should i be able to see the data in
> > > Memory window of CCS 3.3V code composer studio.
> >
> > First you have to say which board you are using. Some boards may have memory chips
> > connected to CE2, some may not. Also it's possible the board was designed so that
> > HPI is enabled, in which case some CE2-related pins are used for HPI.
> >
> > -Jeff
I tried the way suggested by you to write EBSR register...
*((ioport int*)0x6C00 = 0x0001;
So, according to the description of EBSR register, atleast CLKOUT of DSP should get disabled but still at the CLKOUT pin/test point of DSP I am able to observe the 30MHz clock.
So I am feeling that the EBSR register is not getting set.
Regards,
Onkar Patki,
Design Engineer.
----------------------------
Mechatronics Test Equipment (I) Pvt.Ltd.
B, Mayur complex, Opp. Bhelke nagar,
Kothrud, Pune 411 038.
Tel.: 91 20 25386926,27,28,29
Fax:: 91 20 25386930
Mob: 919881730876
Email: m...@vsnl.net
URL: www.mte-india.com
----- Original Message -----
From: Jeff Brower
To: Onkar Patki
Cc: c...
Sent: Thursday, May 15, 2008 10:24 PM
Subject: Re: [c55x] Problem with 5509A address space and CE generation
Onkar-
> Thanks for reply.
>
> I am using 16 bit EMIF bus and I could observe (EMIF_GCTL1,EMIF_CE21 etc )
> registers are getting set properly through Emulator.
>
> Even EBSR @ address 0x6C00 is getting set correctly for full emif mode.
>
> I could not get what do you mean by
> "-your code not enabling EMIF32 bus access by writing to IO space addr
> 0x6c00"
When you write to EBSR (0x6c00), are you doing an I/O port write? The EBSR register
is in onchip mem, but located in I/O space, so you have to use a C code line similar
to:
*((ioport int*)0x6C00) = 1; // enable EMIF32
-Jeff
> ----------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Onkar Patki
> Cc: c...
> Sent: Thursday, May 15, 2008 12:15 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > thanks for the reply.
> > I am working on a customized board where CE1 is connected to FLASH,
> > CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> > it in FULL EMIF mode.
>
> Ok, thanks for explaining.
>
> > On the board, using CRO I am verifying whether CE1,2,3 is getting
> > generated or not.
>
> Ok.
>
> > Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> > getting CE1,2,3 for different addresses, but not for the code I am
> > writing for memory write which is as...
> >
> > long *regdata_SRAM;
> > regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> > *regdata_SRAM = i;// i is any data
> >
> > And with change in address like 0x00200000 , 0x00400000 ,
> > 0x00600000 I am expecting different CE to get generated.
>
> Well it could be a number of things. One thing you might try is code like:
>
> *(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
>
> as that tells the compiler "make this memory write even though the contents are never
> accessed (read)". Otherwise the compiler may ignore the write and not generate the
> actual code.
>
> Other possibilities include:
>
> -your code not enabling EMIF32 bus access
> by writing to IO space addr 0x6c00
>
> -your code not setting correct EMIF registers
> (EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
>
> -you not capturing single CE2 pulses correctly
> on the dig scope (unlike multiple accesses
> or burst of accesses during code download,
> which are easier to see)
>
> -Jeff
>
> > ----------------------
> > Mechatronics Test Equipment (I) Pvt.Ltd.
> > B, Mayur complex, Opp. Bhelke nagar,
> > Kothrud, Pune 411 038.
> > Tel.: 91 20 25386926,27,28,29
> > Fax:: 91 20 25386930
> > Mob: 919881730876
> > Email: m...@vsnl.net
> > URL: www.mte-india.com
> >
> > ----- Original Message -----
> > From: Jeff Brower
> > To: Patki Onkar
> > Cc: c...
> > Sent: Tuesday, May 13, 2008 7:51 PM
> > Subject: Re: [c55x] Problem with 5509A address space and CE generation
> >
> > Onkar-
> >
> > > I am working with TMS320C5509A emif and facing a similar problem.
> >
> > Which board?
> >
> > > When I write address for CE spaces no Chip select is generated.
> >
> > How do you know it's not generated? How do you measure the signal?
> >
> > > By default CE signal for CE space CE1 is generated for any address.
> >
> > There are separate CEn signals on the chip, not just one "CE signal". Look up pins
> > C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> >
> > > I am writing address as shown below.
> > > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config
> > >
> > > Also if I write statement where should i be able to see the data in
> > > Memory window of CCS 3.3V code composer studio.
> >
> > First you have to say which board you are using. Some boards may have memory chips
> > connected to CE2, some may not. Also it's possible the board was designed so that
> > HPI is enabled, in which case some CE2-related pins are used for HPI.
> >
> > -Jeff
Reply by ●May 16, 20082008-05-16
Onkar-
> I tried the way suggested by you to write EBSR register...
> *((ioport int*)0x6C00 = 0x0001;
> So, according to the description of EBSR register, atleast CLKOUT of DSP
> should get disabled but still at the CLKOUT pin/test point of DSP I am
> able to observe the 30MHz clock.
> So I am feeling that the EBSR register is not getting set.
Yes you should be able to do experiments like:
*((ioport int*)0x6C00 <-- disable CLKOUT
...breakpoint, measure CLKOUT on scope, verify
it's disabled
*((ioport int*)0x6C00 <-- enable CLKOUT
...breakpoint, measure CLKOUT again
If that's not working, then I don't know. If the .gel file you are using correctly
sets up CE2 space and SRAM for your board, then your C code should have no trouble.
The only I think I can suggest is that when your code first runs, some code is
running that is doing "something bad", and you haven't found it yet. You might try
putting in the first few asm lang instructions yourself, something like:
NOP
IO write to EBSR
NOP
etc
and use single-step to make the scope measurements. If that works, then you need to
isolate whatever code is causing you problems.
-Jeff
----------------------------
Mechatronics Test Equipment (I) Pvt.Ltd.
B, Mayur complex, Opp. Bhelke nagar,
Kothrud, Pune 411 038.
Tel.: 91 20 25386926,27,28,29
Fax:: 91 20 25386930
Mob: 919881730876
Email: m...@vsnl.net
URL: www.mte-india.com
----- Original Message -----
From: Jeff Brower
To: Onkar Patki
Cc: c...
Sent: Thursday, May 15, 2008 10:24 PM
Subject: Re: [c55x] Problem with 5509A address space and CE generation
Onkar-
> Thanks for reply.
>
> I am using 16 bit EMIF bus and I could observe (EMIF_GCTL1,EMIF_CE21 etc )
> registers are getting set properly through Emulator.
>
> Even EBSR @ address 0x6C00 is getting set correctly for full emif mode.
>
> I could not get what do you mean by
> "-your code not enabling EMIF32 bus access by writing to IO space addr
> 0x6c00"
When you write to EBSR (0x6c00), are you doing an I/O port write? The EBSR
register
is in onchip mem, but located in I/O space, so you have to use a C code line
similar
to:
*((ioport int*)0x6C00) = 1; // enable EMIF32
-Jeff
> ----------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Onkar Patki
> Cc: c...
> Sent: Thursday, May 15, 2008 12:15 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > thanks for the reply.
> > I am working on a customized board where CE1 is connected to FLASH,
> > CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> > it in FULL EMIF mode.
>
> Ok, thanks for explaining.
>
> > On the board, using CRO I am verifying whether CE1,2,3 is getting
> > generated or not.
>
> Ok.
>
> > Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> > getting CE1,2,3 for different addresses, but not for the code I am
> > writing for memory write which is as...
> >
> > long *regdata_SRAM;
> > regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> > *regdata_SRAM = i;// i is any data
> >
> > And with change in address like 0x00200000 , 0x00400000 ,
> > 0x00600000 I am expecting different CE to get generated.
>
> Well it could be a number of things. One thing you might try is code like:
>
> *(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
>
> as that tells the compiler "make this memory write even though the
contents are never
> accessed (read)". Otherwise the compiler may ignore the write and not
generate the
> actual code.
>
> Other possibilities include:
>
> -your code not enabling EMIF32 bus access
> by writing to IO space addr 0x6c00
>
> -your code not setting correct EMIF registers
> (EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
>
> -you not capturing single CE2 pulses correctly
> on the dig scope (unlike multiple accesses
> or burst of accesses during code download,
> which are easier to see)
>
> -Jeff
>
> > ----------------------
> > Mechatronics Test Equipment (I) Pvt.Ltd.
> > B, Mayur complex, Opp. Bhelke nagar,
> > Kothrud, Pune 411 038.
> > Tel.: 91 20 25386926,27,28,29
> > Fax:: 91 20 25386930
> > Mob: 919881730876
> > Email: m...@vsnl.net
> > URL: www.mte-india.com
> >
> > ----- Original Message -----
> > From: Jeff Brower
> > To: Patki Onkar
> > Cc: c...
> > Sent: Tuesday, May 13, 2008 7:51 PM
> > Subject: Re: [c55x] Problem with 5509A address space and CE generation
> >
> > Onkar-
> >
> > > I am working with TMS320C5509A emif and facing a similar problem.
> >
> > Which board?
> >
> > > When I write address for CE spaces no Chip select is generated.
> >
> > How do you know it's not generated? How do you measure the signal?
> >
> > > By default CE signal for CE space CE1 is generated for any address.
> >
> > There are separate CEn signals on the chip, not just one "CE signal".
Look up pins
> > C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> >
> > > I am writing address as shown below.
> > > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode
config
> > >
> > > Also if I write statement where should i be able to see the data in
> > > Memory window of CCS 3.3V code composer studio.
> >
> > First you have to say which board you are using. Some boards may have
memory chips
> > connected to CE2, some may not. Also it's possible the board was
designed so that
> > HPI is enabled, in which case some CE2-related pins are used for HPI.
> >
> > -Jeff
> I tried the way suggested by you to write EBSR register...
> *((ioport int*)0x6C00 = 0x0001;
> So, according to the description of EBSR register, atleast CLKOUT of DSP
> should get disabled but still at the CLKOUT pin/test point of DSP I am
> able to observe the 30MHz clock.
> So I am feeling that the EBSR register is not getting set.
Yes you should be able to do experiments like:
*((ioport int*)0x6C00 <-- disable CLKOUT
...breakpoint, measure CLKOUT on scope, verify
it's disabled
*((ioport int*)0x6C00 <-- enable CLKOUT
...breakpoint, measure CLKOUT again
If that's not working, then I don't know. If the .gel file you are using correctly
sets up CE2 space and SRAM for your board, then your C code should have no trouble.
The only I think I can suggest is that when your code first runs, some code is
running that is doing "something bad", and you haven't found it yet. You might try
putting in the first few asm lang instructions yourself, something like:
NOP
IO write to EBSR
NOP
etc
and use single-step to make the scope measurements. If that works, then you need to
isolate whatever code is causing you problems.
-Jeff
----------------------------
Mechatronics Test Equipment (I) Pvt.Ltd.
B, Mayur complex, Opp. Bhelke nagar,
Kothrud, Pune 411 038.
Tel.: 91 20 25386926,27,28,29
Fax:: 91 20 25386930
Mob: 919881730876
Email: m...@vsnl.net
URL: www.mte-india.com
----- Original Message -----
From: Jeff Brower
To: Onkar Patki
Cc: c...
Sent: Thursday, May 15, 2008 10:24 PM
Subject: Re: [c55x] Problem with 5509A address space and CE generation
Onkar-
> Thanks for reply.
>
> I am using 16 bit EMIF bus and I could observe (EMIF_GCTL1,EMIF_CE21 etc )
> registers are getting set properly through Emulator.
>
> Even EBSR @ address 0x6C00 is getting set correctly for full emif mode.
>
> I could not get what do you mean by
> "-your code not enabling EMIF32 bus access by writing to IO space addr
> 0x6c00"
When you write to EBSR (0x6c00), are you doing an I/O port write? The EBSR
register
is in onchip mem, but located in I/O space, so you have to use a C code line
similar
to:
*((ioport int*)0x6C00) = 1; // enable EMIF32
-Jeff
> ----------------------
> Mechatronics Test Equipment (I) Pvt.Ltd.
> B, Mayur complex, Opp. Bhelke nagar,
> Kothrud, Pune 411 038.
> Tel.: 91 20 25386926,27,28,29
> Fax:: 91 20 25386930
> Mob: 919881730876
> Email: m...@vsnl.net
> URL: www.mte-india.com
>
> ----- Original Message -----
> From: Jeff Brower
> To: Onkar Patki
> Cc: c...
> Sent: Thursday, May 15, 2008 12:15 PM
> Subject: Re: [c55x] Problem with 5509A address space and CE generation
>
> Onkar-
>
> > thanks for the reply.
> > I am working on a customized board where CE1 is connected to FLASH,
> > CE2 is connected to SRAM and CE3 is connected to FPGA. I am using
> > it in FULL EMIF mode.
>
> Ok, thanks for explaining.
>
> > On the board, using CRO I am verifying whether CE1,2,3 is getting
> > generated or not.
>
> Ok.
>
> > Further more, if I use "Load/Save Memory" Utility from CCS3.3 I am
> > getting CE1,2,3 for different addresses, but not for the code I am
> > writing for memory write which is as...
> >
> > long *regdata_SRAM;
> > regdata_SRAM = 0x00400000 ;// CE2 space in word mode
> > *regdata_SRAM = i;// i is any data
> >
> > And with change in address like 0x00200000 , 0x00400000 ,
> > 0x00600000 I am expecting different CE to get generated.
>
> Well it could be a number of things. One thing you might try is code like:
>
> *(volatile int*)0x400000 = 0xFFFF; // put something in CE2 space
>
> as that tells the compiler "make this memory write even though the
contents are never
> accessed (read)". Otherwise the compiler may ignore the write and not
generate the
> actual code.
>
> Other possibilities include:
>
> -your code not enabling EMIF32 bus access
> by writing to IO space addr 0x6c00
>
> -your code not setting correct EMIF registers
> (EMIF_GCTL1, EMIF_GCTL2, EMIF_CE21, etc)
>
> -you not capturing single CE2 pulses correctly
> on the dig scope (unlike multiple accesses
> or burst of accesses during code download,
> which are easier to see)
>
> -Jeff
>
> > ----------------------
> > Mechatronics Test Equipment (I) Pvt.Ltd.
> > B, Mayur complex, Opp. Bhelke nagar,
> > Kothrud, Pune 411 038.
> > Tel.: 91 20 25386926,27,28,29
> > Fax:: 91 20 25386930
> > Mob: 919881730876
> > Email: m...@vsnl.net
> > URL: www.mte-india.com
> >
> > ----- Original Message -----
> > From: Jeff Brower
> > To: Patki Onkar
> > Cc: c...
> > Sent: Tuesday, May 13, 2008 7:51 PM
> > Subject: Re: [c55x] Problem with 5509A address space and CE generation
> >
> > Onkar-
> >
> > > I am working with TMS320C5509A emif and facing a similar problem.
> >
> > Which board?
> >
> > > When I write address for CE spaces no Chip select is generated.
> >
> > How do you know it's not generated? How do you measure the signal?
> >
> > > By default CE signal for CE space CE1 is generated for any address.
> >
> > There are separate CEn signals on the chip, not just one "CE signal".
Look up pins
> > C4-C7 in the 5509A data sheet. Only one is generated at any one time.
> >
> > > I am writing address as shown below.
> > > *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode
config
> > >
> > > Also if I write statement where should i be able to see the data in
> > > Memory window of CCS 3.3V code composer studio.
> >
> > First you have to say which board you are using. Some boards may have
memory chips
> > connected to CE2, some may not. Also it's possible the board was
designed so that
> > HPI is enabled, in which case some CE2-related pins are used for HPI.
> >
> > -Jeff
