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Mcbsp DMA problem

Started by Unknown ●January 25, 2005


Hello,

This code is a modification of some TI code to allow me to
transfer 32 bits over a mcbsp via a DMA. It works fine
for McBSP1 but if I make the changes needed to make it work
for McBSP0 it hangs at the "Wait for DMA transfer to be complete"
loop. (I've noted the mods "wont work"). I'm also a bit confused DMA config structure line.
It looks to me it gets written over later anyway?
0, // (DMA_AdrPtr)(MCBSP_ADDR(DRR10)), /* DMACSSAL */ Thanks for any input

teeretz //===============================================
//===============================================

#include <stdio.h>

#include <csl_mcbsp.h>
#include <csl_dma.h>
#include <csl_irq.h
#ifndef NOP
#define NOP asm( " nop ")
#endif
//---------Global constants---------
#define N 8

//---------Global data definition---------
/* Define transmit and receive buffers */
#pragma DATA_SECTION(rcv,"dmaMem")
Uint32 xmt[N], rcv[N]; MCBSP_Config ConfigLoopBack32= {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_ON, /* DLB = 1 */
MCBSP_SPCR1_RJUST_RZF, /* RJUST = 0 */
MCBSP_SPCR1_CLKSTP_DISABLE, /* CLKSTP = 0 */
MCBSP_SPCR1_DXENA_NA, /* DXENA = 0 */
MCBSP_SPCR1_ABIS_DISABLE, /* ABIS = 0 */
MCBSP_SPCR1_RINTM_RRDY, /* RINTM = 0 */
0, /* RSYNCER = 0 */
MCBSP_SPCR1_RRST_DISABLE /* RRST = 0 */
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO, /* FREE = 0 */
MCBSP_SPCR2_SOFT_NO, /* SOFT = 0 */
MCBSP_SPCR2_FRST_RESET, /* FRST = 0 */
MCBSP_SPCR2_GRST_RESET, /* GRST = 0 */
MCBSP_SPCR2_XINTM_XRDY, /* XINTM = 0 */
0, /* XSYNCER = N/A */
MCBSP_SPCR2_XRST_DISABLE /* XRST = 0 */
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(0), /* RFRLEN1 = 0 */
MCBSP_RCR1_RWDLEN1_32BIT /* RWDLEN1 = 5 */
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, /* RPHASE = 0 */
MCBSP_RCR2_RFRLEN2_OF(0), /* RFRLEN2 = 0 */
MCBSP_RCR2_RWDLEN2_8BIT, /* RWDLEN2 = 0 */
MCBSP_RCR2_RCOMPAND_MSB, /* RCOMPAND = 0 */
MCBSP_RCR2_RFIG_YES, /* RFIG = 0 */
MCBSP_RCR2_RDATDLY_0BIT /* RDATDLY = 0 */
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(0), /* XFRLEN1 = 0 */
MCBSP_XCR1_XWDLEN1_32BIT /* XWDLEN1 = 5 */

),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, /* XPHASE = 0 */
MCBSP_XCR2_XFRLEN2_OF(0), /* XFRLEN2 = 0 */
MCBSP_XCR2_XWDLEN2_8BIT, /* XWDLEN2 = 0 */
MCBSP_XCR2_XCOMPAND_MSB, /* XCOMPAND = 0 */
MCBSP_XCR2_XFIG_YES, /* XFIG = 0 */
MCBSP_XCR2_XDATDLY_0BIT /* XDATDLY = 0 */
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(1), /* FWID = 1 */
MCBSP_SRGR1_CLKGDV_OF(1) /* CLKGDV = 1 */
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE, /* FREE = 0 */
MCBSP_SRGR2_CLKSP_RISING, /* CLKSP = 0 */
MCBSP_SRGR2_CLKSM_INTERNAL, /* CLKSM = 1 */
MCBSP_SRGR2_FSGM_DXR2XSR, /* FSGM = 0 */
MCBSP_SRGR2_FPER_OF(15) /* FPER = 0 */
),
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_RESET, /* IDLEEN = 0 */
MCBSP_PCR_XIOEN_SP, /* XIOEN = 0 */
MCBSP_PCR_RIOEN_SP, /* RIOEN = 0 */
MCBSP_PCR_FSXM_INTERNAL, /* FSXM = 1 */
MCBSP_PCR_FSRM_EXTERNAL, /* FSRM = 0 */
MCBSP_PCR_CLKXM_OUTPUT, /* CLKXM = 1 */
MCBSP_PCR_CLKRM_INPUT, /* CLKRM = 0 */
MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
0, /* DXSTAT = N/A */
MCBSP_PCR_FSXP_ACTIVEHIGH, /* FSXP = 0 */
MCBSP_PCR_FSRP_ACTIVEHIGH, /* FSRP = 0 */
MCBSP_PCR_CLKXP_RISING, /* CLKXP = 0 */
MCBSP_PCR_CLKRP_FALLING /* CLKRP = 0 */
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};

/* Create DMA Receive Side Configuration */
DMA_Config dmaConfig = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_DARAM,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_PERIPH,
DMA_DMACSDP_DATATYPE_32BIT
), /* DMACSDP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_POSTINC,
DMA_DMACCR_SRCAMODE_CONST,
DMA_DMACCR_ENDPROG_ON,
DMA_DMACCR_REPEAT_OFF,
DMA_DMACCR_AUTOINIT_OFF,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_LOW,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_REVT1
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
0, // (DMA_AdrPtr)(MCBSP_ADDR(DRR10)), /* DMACSSAL */
0, /* DMACSSAU */
(DMA_AdrPtr)&rcv, /* DMACDSAL */
0, /* DMACDSAU */
N, /* DMACEN */
1, /* DMACFN */
0, /* DMACFI */
0 /* DMACEI */
};

/* Define a DMA_Handle object to be used with DMA_open function */
DMA_Handle mhDma;

/* Define a MCBSP_Handle object to be used with MCBSP_open function */
MCBSP_Handle mhMcbsp;

volatile Uint16 xfrCnt = 0;
Uint16 err = 0;
Uint16 old_intm;
Uint16 xmtEventId;

//---------Function prototypes---------
/* Protoype for MCBSP transmit interrupt function */
interrupt void mcbspIsr(void);
void taskFxn(void);

//---------main routine---------
void main(void)
{
Uint16 i;
Uint32 kk;

/* Initialize CSL library - This is REQUIRED !!! */
CSL_init();

kk = 0x12345678;

/* Initialize data for transfer */
for (i = 0; i <= N - 1; i++) {
xmt[i] = kk++;

rcv[i] = 0;
}

/* Call function to effect transfer */
taskFxn();
}

void taskFxn(void)
{
Uint16 srcAddrHi, srcAddrLo;
Uint16 dstAddrHi, dstAddrLo;
Uint16 i; // By default, the TMS320C55xx compiler assigns all data symbols word addresses.
// The DMA however, expects all addresses to be byte addresses.
// Therefore, we must shift the address by 2 in order to change the word
// address to a byte address for the DMA transfer.

// works on mcbsp1
srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DRR21))) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DRR21))) << 1) & 0xFFFFu;
// wont work on mcbsp0
// srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DRR20))) >> 15) & 0xFFFFu;
// srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DRR20))) << 1) & 0xFFFFu; dstAddrHi = (Uint16)(((Uint32)(&rcv)) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(&rcv)) << 1) & 0xFFFF; dmaConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaConfig.dmacssau = srcAddrHi;

dmaConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
dmaConfig.dmacdsau = dstAddrHi; /* Open MCBSP Port 1 and set registers to their power on defaults */
// works
mhMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);

// won't work
// mhMcbsp = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET); /* Get interrupt event assoicated MCBSP transmit */
xmtEventId = MCBSP_getXmtEventId(mhMcbsp);

/* Temporarily disable interrupts and clear any pending */
/* interrupts for MCBSP transmit */
old_intm = IRQ_globalDisable();
IRQ_clear(xmtEventId);

/* Enable MCBSP transmit interrupt in IER register */
IRQ_enable(xmtEventId);

/* Set Start Of Interrupt Vector Table */
IRQ_setVecs(0x10000);

/* Place address for MCBSP transmit interrupt service routine */
/* in associated vector location */
IRQ_plug(xmtEventId,&mcbspIsr);

/* Open DMA Channel 2 and set registers to their power on defaults */
mhDma = DMA_open(DMA_CHA2,DMA_OPEN_RESET);

/* Write values from configuration structure to MCBSP control regs */
MCBSP_config(mhMcbsp, &ConfigLoopBack32);

/* Write values from configuration structure to DMA control regs */
DMA_config(mhDma,&dmaConfig);

/* Enable all maskable interrupts */
IRQ_globalEnable();

/* Start MCBSP */
MCBSP_start(mhMcbsp, MCBSP_SRGR_START|MCBSP_SRGR_FRAMESYNC,0x300u);

/* Enable DMA */
DMA_start(mhDma);

/* Take MCBSP transmit annd receive out of reset */
MCBSP_start(mhMcbsp, MCBSP_XMIT_START| MCBSP_RCV_START, 0);

/* Wait for DMA transfer to be complete */
while (!DMA_FGETH(mhDma,DMACSR,FRAME))
{
NOP;
}

/*------*\
* Compare values
\*------*/
for(i = 0; i <= N - 1; i++){
if (rcv[i] != xmt[i]){
++err;
break;
}
}

printf ("%s\n",err?"TEST FAILED" : "TEST PASSED");

/* Restore status of global interrupt enable flag */
IRQ_globalRestore(old_intm);

/* We're done with MCBSP and DMA , so close them */
MCBSP_close(mhMcbsp);
DMA_close(mhDma);
}

/* MCBSP transmit interrupt service routine */
interrupt void mcbspIsr(void) {

if (xfrCnt < N) {
MCBSP_write32(mhMcbsp,xmt[xfrCnt]);
++xfrCnt;
}
else {
MCBSP_FSETH(mhMcbsp,SPCR2,XRST,0);
}
}


Reply by ●January 26, 20052005-01-26
Nevermind,
Missed a setting in DMACCR (Should be DMA_DMACCR_SYNC_REVT0)
Still learning CSL.

I do stand by my comment about the DMACSSAL. It gets written
over later by some fudging to fix byte addressing issues.

For the McBsp one may use
(DMA_AdrPtr)((MCBSP_ADDR(DRR10))<<1), /* DMACSSAL */
in the setup structure and kill off the fix later on.

I found some comments on old posts about TI changing these
structures on without notice? Any more news on the prefered
way to do this?

Thanks

teeretz

>
>Hello,
>
>This code is a modification of some TI code to allow me to
>transfer 32 bits over a mcbsp via a DMA. It works fine
>for McBSP1 but if I make the changes needed to make it work
>for McBSP0 it hangs at the "Wait for DMA transfer to be complete"
>loop. (I've noted the mods "wont work"). >I'm also a bit confused DMA config structure line.
>It looks to me it gets written over later anyway?
>0, // (DMA_AdrPtr)(MCBSP_ADDR(DRR10)), /* DMACSSAL */ >Thanks for any input
>
>teeretz >//===============================================
>//===============================================
>
>#include <stdio.h>
>
>#include <csl_mcbsp.h>
>#include <csl_dma.h>
>#include <csl_irq.h >
>#ifndef NOP
>#define NOP asm( " nop ")
>#endif >
>//---------Global constants---------
>#define N 8
>
>//---------Global data definition---------
>/* Define transmit and receive buffers */
>#pragma DATA_SECTION(rcv,"dmaMem")
>Uint32 xmt[N], rcv[N]; >MCBSP_Config ConfigLoopBack32= {
>MCBSP_SPCR1_RMK(
>MCBSP_SPCR1_DLB_ON, /* DLB = 1 */
>MCBSP_SPCR1_RJUST_RZF, /* RJUST = 0 */
>MCBSP_SPCR1_CLKSTP_DISABLE, /* CLKSTP = 0 */
>MCBSP_SPCR1_DXENA_NA, /* DXENA = 0 */
>MCBSP_SPCR1_ABIS_DISABLE, /* ABIS = 0 */
>MCBSP_SPCR1_RINTM_RRDY, /* RINTM = 0 */
>0, /* RSYNCER = 0 */
>MCBSP_SPCR1_RRST_DISABLE /* RRST = 0 */
>),
>MCBSP_SPCR2_RMK(
>MCBSP_SPCR2_FREE_NO, /* FREE = 0 */
>MCBSP_SPCR2_SOFT_NO, /* SOFT = 0 */
>MCBSP_SPCR2_FRST_RESET, /* FRST = 0 */
>MCBSP_SPCR2_GRST_RESET, /* GRST = 0 */
>MCBSP_SPCR2_XINTM_XRDY, /* XINTM = 0 */
>0, /* XSYNCER = N/A */
>MCBSP_SPCR2_XRST_DISABLE /* XRST = 0 */
>),
>MCBSP_RCR1_RMK(
>MCBSP_RCR1_RFRLEN1_OF(0), /* RFRLEN1 = 0 */
>MCBSP_RCR1_RWDLEN1_32BIT /* RWDLEN1 = 5 */
>),
>MCBSP_RCR2_RMK(
>MCBSP_RCR2_RPHASE_SINGLE, /* RPHASE = 0 */
>MCBSP_RCR2_RFRLEN2_OF(0), /* RFRLEN2 = 0 */
>MCBSP_RCR2_RWDLEN2_8BIT, /* RWDLEN2 = 0 */
>MCBSP_RCR2_RCOMPAND_MSB, /* RCOMPAND = 0 */
>MCBSP_RCR2_RFIG_YES, /* RFIG = 0 */
>MCBSP_RCR2_RDATDLY_0BIT /* RDATDLY = 0 */
>),
>MCBSP_XCR1_RMK(
>MCBSP_XCR1_XFRLEN1_OF(0), /* XFRLEN1 = 0 */
>MCBSP_XCR1_XWDLEN1_32BIT /* XWDLEN1 = 5 */
>
>),
>MCBSP_XCR2_RMK(
>MCBSP_XCR2_XPHASE_SINGLE, /* XPHASE = 0 */
>MCBSP_XCR2_XFRLEN2_OF(0), /* XFRLEN2 = 0 */
>MCBSP_XCR2_XWDLEN2_8BIT, /* XWDLEN2 = 0 */
>MCBSP_XCR2_XCOMPAND_MSB, /* XCOMPAND = 0 */
>MCBSP_XCR2_XFIG_YES, /* XFIG = 0 */
>MCBSP_XCR2_XDATDLY_0BIT /* XDATDLY = 0 */
>),
>MCBSP_SRGR1_RMK(
>MCBSP_SRGR1_FWID_OF(1), /* FWID = 1 */
>MCBSP_SRGR1_CLKGDV_OF(1) /* CLKGDV = 1 */
>),
>MCBSP_SRGR2_RMK(
>MCBSP_SRGR2_GSYNC_FREE, /* FREE = 0 */
>MCBSP_SRGR2_CLKSP_RISING, /* CLKSP = 0 */
>MCBSP_SRGR2_CLKSM_INTERNAL, /* CLKSM = 1 */
>MCBSP_SRGR2_FSGM_DXR2XSR, /* FSGM = 0 */
>MCBSP_SRGR2_FPER_OF(15) /* FPER = 0 */
>),
>MCBSP_MCR1_DEFAULT,
>MCBSP_MCR2_DEFAULT,
>MCBSP_PCR_RMK(
>MCBSP_PCR_IDLEEN_RESET, /* IDLEEN = 0 */
>MCBSP_PCR_XIOEN_SP, /* XIOEN = 0 */
>MCBSP_PCR_RIOEN_SP, /* RIOEN = 0 */
>MCBSP_PCR_FSXM_INTERNAL, /* FSXM = 1 */
>MCBSP_PCR_FSRM_EXTERNAL, /* FSRM = 0 */
>MCBSP_PCR_CLKXM_OUTPUT, /* CLKXM = 1 */
>MCBSP_PCR_CLKRM_INPUT, /* CLKRM = 0 */
>MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
>0, /* DXSTAT = N/A */
>MCBSP_PCR_FSXP_ACTIVEHIGH, /* FSXP = 0 */
>MCBSP_PCR_FSRP_ACTIVEHIGH, /* FSRP = 0 */
>MCBSP_PCR_CLKXP_RISING, /* CLKXP = 0 */
>MCBSP_PCR_CLKRP_FALLING /* CLKRP = 0 */
>),
>MCBSP_RCERA_DEFAULT,
>MCBSP_RCERB_DEFAULT,
>MCBSP_RCERC_DEFAULT,
>MCBSP_RCERD_DEFAULT,
>MCBSP_RCERE_DEFAULT,
>MCBSP_RCERF_DEFAULT,
>MCBSP_RCERG_DEFAULT,
>MCBSP_RCERH_DEFAULT,
>MCBSP_XCERA_DEFAULT,
>MCBSP_XCERB_DEFAULT,
>MCBSP_XCERC_DEFAULT,
>MCBSP_XCERD_DEFAULT,
>MCBSP_XCERE_DEFAULT,
>MCBSP_XCERF_DEFAULT,
>MCBSP_XCERG_DEFAULT,
>MCBSP_XCERH_DEFAULT
>};
>
>/* Create DMA Receive Side Configuration */
>DMA_Config dmaConfig = {
>DMA_DMACSDP_RMK(
>DMA_DMACSDP_DSTBEN_NOBURST,
>DMA_DMACSDP_DSTPACK_OFF,
>DMA_DMACSDP_DST_DARAM,
>DMA_DMACSDP_SRCBEN_NOBURST,
>DMA_DMACSDP_SRCPACK_OFF,
>DMA_DMACSDP_SRC_PERIPH,
>DMA_DMACSDP_DATATYPE_32BIT
>), /* DMACSDP */
>DMA_DMACCR_RMK(
>DMA_DMACCR_DSTAMODE_POSTINC,
>DMA_DMACCR_SRCAMODE_CONST,
>DMA_DMACCR_ENDPROG_ON,
>DMA_DMACCR_REPEAT_OFF,
>DMA_DMACCR_AUTOINIT_OFF,
>DMA_DMACCR_EN_STOP,
>DMA_DMACCR_PRIO_LOW,
>DMA_DMACCR_FS_DISABLE,
>DMA_DMACCR_SYNC_REVT1
>), /* DMACCR */
>DMA_DMACICR_RMK(
>DMA_DMACICR_BLOCKIE_OFF,
>DMA_DMACICR_LASTIE_OFF,
>DMA_DMACICR_FRAMEIE_ON,
>DMA_DMACICR_FIRSTHALFIE_OFF,
>DMA_DMACICR_DROPIE_OFF,
>DMA_DMACICR_TIMEOUTIE_OFF
>), /* DMACICR */
>0, // (DMA_AdrPtr)(MCBSP_ADDR(DRR10)), /* DMACSSAL */
>0, /* DMACSSAU */
>(DMA_AdrPtr)&rcv, /* DMACDSAL */
>0, /* DMACDSAU */
>N, /* DMACEN */
>1, /* DMACFN */
>0, /* DMACFI */
>0 /* DMACEI */
>};
>
>/* Define a DMA_Handle object to be used with DMA_open function */
>DMA_Handle mhDma;
>
>/* Define a MCBSP_Handle object to be used with MCBSP_open function */
>MCBSP_Handle mhMcbsp;
>
>volatile Uint16 xfrCnt = 0;
>Uint16 err = 0;
>Uint16 old_intm;
>Uint16 xmtEventId;
>
>//---------Function prototypes---------
>/* Protoype for MCBSP transmit interrupt function */
>interrupt void mcbspIsr(void);
>void taskFxn(void);
>
>//---------main routine---------
>void main(void)
>{
>Uint16 i;
>Uint32 kk;
>
>/* Initialize CSL library - This is REQUIRED !!! */
>CSL_init();
>
>kk = 0x12345678;
>
>/* Initialize data for transfer */
>for (i = 0; i <= N - 1; i++) {
>xmt[i] = kk++;
>
>rcv[i] = 0;
>}
>
>/* Call function to effect transfer */
>taskFxn();
>}
>
>void taskFxn(void)
>{
>Uint16 srcAddrHi, srcAddrLo;
>Uint16 dstAddrHi, dstAddrLo;
>Uint16 i; >// By default, the TMS320C55xx compiler assigns all data symbols word addresses.
>// The DMA however, expects all addresses to be byte addresses.
>// Therefore, we must shift the address by 2 in order to change the word
>// address to a byte address for the DMA transfer.
>
>// works on mcbsp1
>srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DRR21))) >> 15) & 0xFFFFu;
>srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DRR21))) << 1) & 0xFFFFu;
>// wont work on mcbsp0
>// srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DRR20))) >> 15) & 0xFFFFu;
>// srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DRR20))) << 1) & 0xFFFFu; >dstAddrHi = (Uint16)(((Uint32)(&rcv)) >> 15) & 0xFFFFu;
>dstAddrLo = (Uint16)(((Uint32)(&rcv)) << 1) & 0xFFFF; >dmaConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
>dmaConfig.dmacssau = srcAddrHi;
>
>dmaConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
>dmaConfig.dmacdsau = dstAddrHi; >/* Open MCBSP Port 1 and set registers to their power on defaults */
>// works
>mhMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
>
>// won't work
>// mhMcbsp = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET); >/* Get interrupt event assoicated MCBSP transmit */
>xmtEventId = MCBSP_getXmtEventId(mhMcbsp);
>
>/* Temporarily disable interrupts and clear any pending */
>/* interrupts for MCBSP transmit */
>old_intm = IRQ_globalDisable();
>IRQ_clear(xmtEventId);
>
>/* Enable MCBSP transmit interrupt in IER register */
>IRQ_enable(xmtEventId);
>
>/* Set Start Of Interrupt Vector Table */
>IRQ_setVecs(0x10000);
>
>/* Place address for MCBSP transmit interrupt service routine */
>/* in associated vector location */
>IRQ_plug(xmtEventId,&mcbspIsr);
>
>/* Open DMA Channel 2 and set registers to their power on defaults */
>mhDma = DMA_open(DMA_CHA2,DMA_OPEN_RESET);
>
>/* Write values from configuration structure to MCBSP control regs */
>MCBSP_config(mhMcbsp, &ConfigLoopBack32);
>
>/* Write values from configuration structure to DMA control regs */
>DMA_config(mhDma,&dmaConfig);
>
>/* Enable all maskable interrupts */
>IRQ_globalEnable();
>
>/* Start MCBSP */
>MCBSP_start(mhMcbsp, MCBSP_SRGR_START|MCBSP_SRGR_FRAMESYNC,0x300u);
>
>/* Enable DMA */
>DMA_start(mhDma);
>
>/* Take MCBSP transmit annd receive out of reset */
>MCBSP_start(mhMcbsp, MCBSP_XMIT_START| MCBSP_RCV_START, 0);
>
>/* Wait for DMA transfer to be complete */
>while (!DMA_FGETH(mhDma,DMACSR,FRAME))
>{
>NOP;
>}
>
>/*------*\
>* Compare values
>\*------*/
>for(i = 0; i <= N - 1; i++){
>if (rcv[i] != xmt[i]){
>++err;
>break;
>}
>}
>
>printf ("%s\n",err?"TEST FAILED" : "TEST PASSED");
>
>/* Restore status of global interrupt enable flag */
>IRQ_globalRestore(old_intm);
>
>/* We're done with MCBSP and DMA , so close them */
>MCBSP_close(mhMcbsp);
>DMA_close(mhDma);
>}
>
>/* MCBSP transmit interrupt service routine */
>interrupt void mcbspIsr(void) {
>
>if (xfrCnt < N) {
>MCBSP_write32(mhMcbsp,xmt[xfrCnt]);
>++xfrCnt;
>}
>else {
>MCBSP_FSETH(mhMcbsp,SPCR2,XRST,0);
>}
>} >


Reply by dileepan_c ●January 27, 20052005-01-27

hi,

you can always download and use the latest CSL from the following
link:

yes, there were kot of bugs in the csl and they had corrected it and
released periodically. test with the latest csl and see how it works.
http://focus.ti.com/docs/toolsw/folders/print/sprc133.html

i have one basic doubt: for 32 bit mcbsp transfer, you need to read
from DRR2 first and then from DRR1. How will the dma do this? if you
fix the receive side dma source as a fixed one with DRR1 register,
how dma will read from DRR2 register?

which processor are you using?

regards,
Dileepan.
--- In , teeretz@y... wrote:
> Nevermind,
> Missed a setting in DMACCR (Should be DMA_DMACCR_SYNC_REVT0)
> Still learning CSL.
>
> I do stand by my comment about the DMACSSAL. It gets written
> over later by some fudging to fix byte addressing issues.
>
> For the McBsp one may use
> (DMA_AdrPtr)((MCBSP_ADDR(DRR10))<<1), /* DMACSSAL */
> in the setup structure and kill off the fix later on.
>
> I found some comments on old posts about TI changing these
> structures on without notice? Any more news on the prefered
> way to do this?
>
> Thanks
>
> teeretz
>
> >
> >Hello,
> >
> >This code is a modification of some TI code to allow me to
> >transfer 32 bits over a mcbsp via a DMA. It works fine
> >for McBSP1 but if I make the changes needed to make it work
> >for McBSP0 it hangs at the "Wait for DMA transfer to be complete"
> >loop. (I've noted the mods "wont work").
> >
> >
> >I'm also a bit confused DMA config structure line.
> >It looks to me it gets written over later anyway?
> >0, // (DMA_AdrPtr)(MCBSP_ADDR(DRR10)), /* DMACSSAL */
> >
> >
> >Thanks for any input
> >
> >teeretz
> >
> >
> >//===============================================
> >//===============================================
> >
> >#include <stdio.h>
> >
> >#include <csl_mcbsp.h>
> >#include <csl_dma.h>
> >#include <csl_irq.h>
> >
> >
> >
> >#ifndef NOP
> >#define NOP asm( " nop ")
> >#endif
> >
> >
> >
> >//---------Global constants---------
> >#define N 8
> >
> >//---------Global data definition---------
> >/* Define transmit and receive buffers */
> >#pragma DATA_SECTION(rcv,"dmaMem")
> >Uint32 xmt[N], rcv[N];
> >
> >
> >MCBSP_Config ConfigLoopBack32= {
> >MCBSP_SPCR1_RMK(
> >MCBSP_SPCR1_DLB_ON, /* DLB = 1 */
> >MCBSP_SPCR1_RJUST_RZF, /* RJUST = 0 */
> >MCBSP_SPCR1_CLKSTP_DISABLE, /* CLKSTP = 0 */
> >MCBSP_SPCR1_DXENA_NA, /* DXENA = 0 */
> >MCBSP_SPCR1_ABIS_DISABLE, /* ABIS = 0 */
> >MCBSP_SPCR1_RINTM_RRDY, /* RINTM = 0 */
> >0, /* RSYNCER = 0 */
> >MCBSP_SPCR1_RRST_DISABLE /* RRST = 0 */
> >),
> >MCBSP_SPCR2_RMK(
> >MCBSP_SPCR2_FREE_NO, /* FREE = 0 */
> >MCBSP_SPCR2_SOFT_NO, /* SOFT = 0 */
> >MCBSP_SPCR2_FRST_RESET, /* FRST = 0 */
> >MCBSP_SPCR2_GRST_RESET, /* GRST = 0 */
> >MCBSP_SPCR2_XINTM_XRDY, /* XINTM = 0 */
> >0, /* XSYNCER = N/A */
> >MCBSP_SPCR2_XRST_DISABLE /* XRST = 0 */
> >),
> >MCBSP_RCR1_RMK(
> >MCBSP_RCR1_RFRLEN1_OF(0), /* RFRLEN1 = 0 */
> >MCBSP_RCR1_RWDLEN1_32BIT /* RWDLEN1 = 5 */
> >),
> >MCBSP_RCR2_RMK(
> >MCBSP_RCR2_RPHASE_SINGLE, /* RPHASE = 0 */
> >MCBSP_RCR2_RFRLEN2_OF(0), /* RFRLEN2 = 0 */
> >MCBSP_RCR2_RWDLEN2_8BIT, /* RWDLEN2 = 0 */
> >MCBSP_RCR2_RCOMPAND_MSB, /* RCOMPAND = 0 */
> >MCBSP_RCR2_RFIG_YES, /* RFIG = 0 */
> >MCBSP_RCR2_RDATDLY_0BIT /* RDATDLY = 0 */
> >),
> >MCBSP_XCR1_RMK(
> >MCBSP_XCR1_XFRLEN1_OF(0), /* XFRLEN1 = 0 */
> >MCBSP_XCR1_XWDLEN1_32BIT /* XWDLEN1 = 5 */
> >
> >),
> >MCBSP_XCR2_RMK(
> >MCBSP_XCR2_XPHASE_SINGLE, /* XPHASE = 0 */
> >MCBSP_XCR2_XFRLEN2_OF(0), /* XFRLEN2 = 0 */
> >MCBSP_XCR2_XWDLEN2_8BIT, /* XWDLEN2 = 0 */
> >MCBSP_XCR2_XCOMPAND_MSB, /* XCOMPAND = 0 */
> >MCBSP_XCR2_XFIG_YES, /* XFIG = 0 */
> >MCBSP_XCR2_XDATDLY_0BIT /* XDATDLY = 0 */
> >),
> >MCBSP_SRGR1_RMK(
> >MCBSP_SRGR1_FWID_OF(1), /* FWID = 1 */
> >MCBSP_SRGR1_CLKGDV_OF(1) /* CLKGDV = 1 */
> >),
> >MCBSP_SRGR2_RMK(
> >MCBSP_SRGR2_GSYNC_FREE, /* FREE = 0 */
> >MCBSP_SRGR2_CLKSP_RISING, /* CLKSP = 0 */
> >MCBSP_SRGR2_CLKSM_INTERNAL, /* CLKSM = 1 */
> >MCBSP_SRGR2_FSGM_DXR2XSR, /* FSGM = 0 */
> >MCBSP_SRGR2_FPER_OF(15) /* FPER = 0 */
> >),
> >MCBSP_MCR1_DEFAULT,
> >MCBSP_MCR2_DEFAULT,
> >MCBSP_PCR_RMK(
> >MCBSP_PCR_IDLEEN_RESET, /* IDLEEN = 0 */
> >MCBSP_PCR_XIOEN_SP, /* XIOEN = 0 */
> >MCBSP_PCR_RIOEN_SP, /* RIOEN = 0 */
> >MCBSP_PCR_FSXM_INTERNAL, /* FSXM = 1 */
> >MCBSP_PCR_FSRM_EXTERNAL, /* FSRM = 0 */
> >MCBSP_PCR_CLKXM_OUTPUT, /* CLKXM = 1 */
> >MCBSP_PCR_CLKRM_INPUT, /* CLKRM = 0 */
> >MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
> >0, /* DXSTAT = N/A */
> >MCBSP_PCR_FSXP_ACTIVEHIGH, /* FSXP = 0 */
> >MCBSP_PCR_FSRP_ACTIVEHIGH, /* FSRP = 0 */
> >MCBSP_PCR_CLKXP_RISING, /* CLKXP = 0 */
> >MCBSP_PCR_CLKRP_FALLING /* CLKRP = 0 */
> >),
> >MCBSP_RCERA_DEFAULT,
> >MCBSP_RCERB_DEFAULT,
> >MCBSP_RCERC_DEFAULT,
> >MCBSP_RCERD_DEFAULT,
> >MCBSP_RCERE_DEFAULT,
> >MCBSP_RCERF_DEFAULT,
> >MCBSP_RCERG_DEFAULT,
> >MCBSP_RCERH_DEFAULT,
> >MCBSP_XCERA_DEFAULT,
> >MCBSP_XCERB_DEFAULT,
> >MCBSP_XCERC_DEFAULT,
> >MCBSP_XCERD_DEFAULT,
> >MCBSP_XCERE_DEFAULT,
> >MCBSP_XCERF_DEFAULT,
> >MCBSP_XCERG_DEFAULT,
> >MCBSP_XCERH_DEFAULT
> >};
> >
> >/* Create DMA Receive Side Configuration */
> >DMA_Config dmaConfig = {
> >DMA_DMACSDP_RMK(
> >DMA_DMACSDP_DSTBEN_NOBURST,
> >DMA_DMACSDP_DSTPACK_OFF,
> >DMA_DMACSDP_DST_DARAM,
> >DMA_DMACSDP_SRCBEN_NOBURST,
> >DMA_DMACSDP_SRCPACK_OFF,
> >DMA_DMACSDP_SRC_PERIPH,
> >DMA_DMACSDP_DATATYPE_32BIT
> >), /* DMACSDP */
> >DMA_DMACCR_RMK(
> >DMA_DMACCR_DSTAMODE_POSTINC,
> >DMA_DMACCR_SRCAMODE_CONST,
> >DMA_DMACCR_ENDPROG_ON,
> >DMA_DMACCR_REPEAT_OFF,
> >DMA_DMACCR_AUTOINIT_OFF,
> >DMA_DMACCR_EN_STOP,
> >DMA_DMACCR_PRIO_LOW,
> >DMA_DMACCR_FS_DISABLE,
> >DMA_DMACCR_SYNC_REVT1
> >), /* DMACCR */
> >DMA_DMACICR_RMK(
> >DMA_DMACICR_BLOCKIE_OFF,
> >DMA_DMACICR_LASTIE_OFF,
> >DMA_DMACICR_FRAMEIE_ON,
> >DMA_DMACICR_FIRSTHALFIE_OFF,
> >DMA_DMACICR_DROPIE_OFF,
> >DMA_DMACICR_TIMEOUTIE_OFF
> >), /* DMACICR */
> >0, // (DMA_AdrPtr)(MCBSP_ADDR(DRR10)), /* DMACSSAL */
> >0, /* DMACSSAU */
> >(DMA_AdrPtr)&rcv, /* DMACDSAL */
> >0, /* DMACDSAU */
> >N, /* DMACEN */
> >1, /* DMACFN */
> >0, /* DMACFI */
> >0 /* DMACEI */
> >};
> >
> >/* Define a DMA_Handle object to be used with DMA_open function
*/
> >DMA_Handle mhDma;
> >
> >/* Define a MCBSP_Handle object to be used with MCBSP_open
function */
> >MCBSP_Handle mhMcbsp;
> >
> >volatile Uint16 xfrCnt = 0;
> >Uint16 err = 0;
> >Uint16 old_intm;
> >Uint16 xmtEventId;
> >
> >//---------Function prototypes---------
> >/* Protoype for MCBSP transmit interrupt function */
> >interrupt void mcbspIsr(void);
> >void taskFxn(void);
> >
> >//---------main routine---------
> >void main(void)
> >{
> >Uint16 i;
> >Uint32 kk;
> >
> >/* Initialize CSL library - This is REQUIRED !!! */
> >CSL_init();
> >
> >kk = 0x12345678;
> >
> >/* Initialize data for transfer */
> >for (i = 0; i <= N - 1; i++) {
> >xmt[i] = kk++;
> >
> >rcv[i] = 0;
> >}
> >
> >/* Call function to effect transfer */
> >taskFxn();
> >}
> >
> >void taskFxn(void)
> >{
> >Uint16 srcAddrHi, srcAddrLo;
> >Uint16 dstAddrHi, dstAddrLo;
> >Uint16 i;
> >
> >
> >// By default, the TMS320C55xx compiler assigns all data symbols
word addresses.
> >// The DMA however, expects all addresses to be byte addresses.
> >// Therefore, we must shift the address by 2 in order to change
the word
> >// address to a byte address for the DMA transfer.
> >
> >// works on mcbsp1
> >srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DRR21))) >> 15) &
0xFFFFu;
> >srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DRR21))) << 1) &
0xFFFFu;
> >// wont work on mcbsp0
> >// srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DRR20))) >> 15) &
0xFFFFu;
> >// srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DRR20))) << 1) &
0xFFFFu;
> >
> >
> >dstAddrHi = (Uint16)(((Uint32)(&rcv)) >> 15) & 0xFFFFu;
> >dstAddrLo = (Uint16)(((Uint32)(&rcv)) << 1) & 0xFFFF;
> >
> >
> >dmaConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
> >dmaConfig.dmacssau = srcAddrHi;
> >
> >dmaConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
> >dmaConfig.dmacdsau = dstAddrHi;
> >
> >
> >/* Open MCBSP Port 1 and set registers to their power on defaults
*/
> >// works
> >mhMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
> >
> >// won't work
> >// mhMcbsp = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
> >
> >
> >/* Get interrupt event assoicated MCBSP transmit */
> >xmtEventId = MCBSP_getXmtEventId(mhMcbsp);
> >
> >/* Temporarily disable interrupts and clear any pending */
> >/* interrupts for MCBSP transmit */
> >old_intm = IRQ_globalDisable();
> >IRQ_clear(xmtEventId);
> >
> >/* Enable MCBSP transmit interrupt in IER register */
> >IRQ_enable(xmtEventId);
> >
> >/* Set Start Of Interrupt Vector Table */
> >IRQ_setVecs(0x10000);
> >
> >/* Place address for MCBSP transmit interrupt service routine */
> >/* in associated vector location */
> >IRQ_plug(xmtEventId,&mcbspIsr);
> >
> >/* Open DMA Channel 2 and set registers to their power on defaults
*/
> >mhDma = DMA_open(DMA_CHA2,DMA_OPEN_RESET);
> >
> >/* Write values from configuration structure to MCBSP control regs
*/
> >MCBSP_config(mhMcbsp, &ConfigLoopBack32);
> >
> >/* Write values from configuration structure to DMA control regs
*/
> >DMA_config(mhDma,&dmaConfig);
> >
> >/* Enable all maskable interrupts */
> >IRQ_globalEnable();
> >
> >/* Start MCBSP */
> >MCBSP_start(mhMcbsp,
MCBSP_SRGR_START|MCBSP_SRGR_FRAMESYNC,0x300u);
> >
> >/* Enable DMA */
> >DMA_start(mhDma);
> >
> >/* Take MCBSP transmit annd receive out of reset */
> >MCBSP_start(mhMcbsp, MCBSP_XMIT_START| MCBSP_RCV_START, 0);
> >
> >/* Wait for DMA transfer to be complete */
> >while (!DMA_FGETH(mhDma,DMACSR,FRAME))
> >{
> >NOP;
> >}
> >
> >/*------*\
> >* Compare values
> >\*------*/
> >for(i = 0; i <= N - 1; i++){
> >if (rcv[i] != xmt[i]){
> >++err;
> >break;
> >}
> >}
> >
> >printf ("%s\n",err?"TEST FAILED" : "TEST PASSED");
> >
> >/* Restore status of global interrupt enable flag */
> >IRQ_globalRestore(old_intm);
> >
> >/* We're done with MCBSP and DMA , so close them */
> >MCBSP_close(mhMcbsp);
> >DMA_close(mhDma);
> >}
> >
> >/* MCBSP transmit interrupt service routine */
> >interrupt void mcbspIsr(void) {
> >
> >if (xfrCnt < N) {
> >MCBSP_write32(mhMcbsp,xmt[xfrCnt]);
> >++xfrCnt;
> >}
> >else {
> >MCBSP_FSETH(mhMcbsp,SPCR2,XRST,0);
> >}
> >}
> >
> >
> >
> >
> >
> >
> >
> >
> >


Reply by ●January 27, 20052005-01-27


Thanks for the input,

Processor is the 5509a.

I hesitate to upgrade the CSL wo a lot of testing. We spent
a lot of time getting the SD and USB interfaces working and
don't want to break them.

The DMA is set up for 32 bits. I asked your very question
about the DRR2 / DRR1 order few days ago but it
did not appear in the 55x group for some reason.

Rather than ask again & wait. I tried both ways.
DRR2 seems to work.

I should also add that my adding the
(DMA_AdrPtr)((MCBSP_ADDR(DRR10))<<1),
to the DMA structure will probably only work for on chip
perpf's like the McBSP with upper address of 0x0000?

So TI's method is more generic? teeretz >
>hi,
>
>you can always download and use the latest CSL from the following
>link:
>
>yes, there were kot of bugs in the csl and they had corrected it and
>released periodically. test with the latest csl and see how it works.
> http://focus.ti.com/docs/toolsw/folders/print/sprc133.html
>
>i have one basic doubt: for 32 bit mcbsp transfer, you need to read
>from DRR2 first and then from DRR1. How will the dma do this? if you
>fix the receive side dma source as a fixed one with DRR1 register,
>how dma will read from DRR2 register?
>
>which processor are you using?
>
>regards,
>Dileepan.
>--- In , teeretz@y... wrote:
>>
>>
>>
>> Nevermind,
>> Missed a setting in DMACCR (Should be DMA_DMACCR_SYNC_REVT0)
>> Still learning CSL.
>>
>> I do stand by my comment about the DMACSSAL. It gets written
>> over later by some fudging to fix byte addressing issues.
>>
>> For the McBsp one may use
>> (DMA_AdrPtr)((MCBSP_ADDR(DRR10))<<1), /* DMACSSAL */
>> in the setup structure and kill off the fix later on.
>>
>> I found some comments on old posts about TI changing these
>> structures on without notice? Any more news on the prefered
>> way to do this?
>>
>> Thanks
>>
>> teeretz
>>




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