C6x11 DSK and L2 Cache

Started by cbdogbert September 15, 2002
Hello all,

I have run into something of a conundrum with my C6211 DSK board.
I am using an area in lower onchip memory for program instructions,
and attempting to use the rest of the memory for two large data
buffers. I am finding that writing to areas in the 0xC200 -> 0xE800
range cause seriously undesired operations. The entire processor
does not halt, but the code no longer runs. Common sense tells me
that I am writing over L2 cache, but I have checked to ensure that L2
cache is not present in the 0xC000 -> 0xFFFF area by looking at the
L2MODE bitfield in the CCFG. L2MODE is set to 000b (all onchip
memory is SRAM, none is used for cache).

Has anyone else experienced an issue such as this? It is awfully
suspicious that the SRAM exhibits this kind of behavior here (so
close to the 0xC000 boundary in one of the L2 cache modes).

If anyone is interested in my MAP file, I'll post it too.

Thanks for any help,

Don Eubanks
DSP Systems Engineer
Signalogic, Inc.