McBSP SPI Slave Tx and Rx

I have configured McBSP0 as a slave to talk to my external Master. I used 4 pins, CLK, SO, SI, and SS as frame sync for McBSP. I do not have any issue receving data from Master. However I am haveing some trouble in downloading data to Master. Seems losing data.

I configure EDMA to trasfer data from McBSP receive register to a buffer in memory. However I Did not configure any EDMA channel for Transmission event. In order to transmit a word from McBSP I used polling method to watch XRDY pin of SPCR and write the DXR register to shift the data out.

My question is:

Can anyone tell me if I have to configure any EDMA channel in order to use the pulling method I am using.

Any help will be appreciated.

Thanks

Sankar Start a New Thread

Sankar,

On Tue, Nov 11, 2008 at 8:36 AM, wrote:
> I have configured McBSP0 as a slave to talk to my external Master. I used 4
> pins, CLK, SO, SI, and SS as frame sync for McBSP. I do not have any issue
> receving data from Master. However I am haveing some trouble in downloading
> data to Master. Seems losing data.
>
> I configure EDMA to trasfer data from McBSP receive register to a buffer in
> memory. However I Did not configure any EDMA channel for Transmission event.
> In order to transmit a word from McBSP I used polling method to watch XRDY
> pin of SPCR and write the DXR register to shift the data out.
>
> My question is:
>
> Can anyone tell me if I have to configure any EDMA channel in order to use
> the pulling method I am using.


You do not need EDMA - polling will work if you poll the correct bit.
1. What is the data rate??
2. What type and speed are the master and slave??
3. If the clock rate is in the Mhz range, have you tried to slow it
down?? [or put a delay between frames]
4. Is the master missing entire frames?? or 'parts of frames'??

mikedunn
>
> Any help will be appreciated.
>
> Thanks
>
> Sankar

--
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sanjarbarua,

Actually, since the DSP is configured as slave, it must wait for the master to
request data (then the master is expecting the data).
The first thing sent to the master should inform the master as to how much data
will be sent, even if that count is 0.

R. Williams
---------- Original Message -----------
From: s...@hotmail.com
To: c...
Sent: Tue, 11 Nov 2008 09:36:13 -0500
Subject: [c6x] McBSP SPI Slave Tx and Rx

> I have configured McBSP0 as a slave to talk to my external Master. I
> used 4 pins, CLK, SO, SI, and SS as frame sync for McBSP. I do not
> have any issue receving data from Master. However I am haveing some
> trouble in downloading data to Master. Seems losing data.
>
> I configure EDMA to trasfer data from McBSP receive register to a
> buffer in memory. However I Did not configure any EDMA channel for
> Transmission event. In order to transmit a word from McBSP I used
> polling method to watch XRDY pin of SPCR and write the DXR register to
> shift the data out.
>
> My question is:
>
> Can anyone tell me if I have to configure any EDMA channel in order to
> use the pulling method I am using.
>
> Any help will be appreciated.
>
> Thanks
>
> Sankar
------- End of Original Message ------- Start a New Thread

Mike,

Thanks a lot for your quick response. My SPI clock speed is 1 MHz. DSP is running at 150 MHz and McBSP0 at 75 MHz.

1. What is the data rate -> 15KBytes per sec
2. What type and speed are the master and slave -> Master at 32 MHz, Slave at 150 MHz. SPI is configured at 1 MHz speed
3. If the clock rate is in the Mhz range, have you tried to slow it
down?? [or put a delay between frames]-> 1 Bit delay per frame
4. Is the master missing entire frames?? or 'parts of frames'??

This is the senario of my application:

Master sends 17 Bytes /1.1ms interval where at the end there are some 150 us idle time.

During 150 us Idle time, master produces an interrupt for a 4 byte long word data to be downloaded from slave to master. System can not afford to lose any word. Evey 1.1 ms time interval, Master must receive a valid word until all data is sent out. In this way Slave sends out 8 packet of data of 200 byte long each. So I have to send 50 words in consecutive 50 1.1 ms intervals.

I configured an interrupt routine to send out the word. Immediate after sending a word, i write 0 to DXR again. so that all byte out is 0 except the valid byte.

Here are the problems what I am seeing:

1. If I send all 50 words are same value (any), it seems Master receive all and validate with checksum.

I could not find an rational for what I am seeing:

I have configured McBSP0 as a slave to talk to my external Master. I used 4 pins, CLK, SO, SI, and SS as frame sync for McBSP. I do not have any issue receving data from Master. However I am haveing some trouble in downloading data to Master. Seems losing data.
>
>I configure EDMA to trasfer data from McBSP receive register to a buffer in memory. However I Did not configure any EDMA channel for Transmission event. In order to transmit a word from McBSP I used polling method to watch XRDY pin of SPCR and write the DXR register to shift the data out.
>
>My question is:
>
>Can anyone tell me if I have to configure any EDMA channel in order to use the pulling method I am using.
>
>Any help will be appreciated.
>
>Thanks
>
>Sankar
> Start a New Thread

sankar,

Given that the slave McBSP is writing many 0x00 bytes between the valid data
bytes, how is the master to distinguish between a 'idle' 0x00 byte and a valid
data byte, especially if the valid data byte is also 0x00.

a better move would be to only send valid data bytes. Then the master can
receive/process each and every received byte.

R. Williams

---------- Original Message -----------
From: s...@hotmail.com
To: c...
Sent: Tue, 11 Nov 2008 14:36:00 -0500
Subject: [c6x] Re: McBSP SPI Slave Tx and Rx

> Mike,
>
> Thanks a lot for your quick response. My SPI clock speed is 1 MHz.
> DSP is running at 150 MHz and McBSP0 at 75 MHz.
>
> 1. What is the data rate -> 15KBytes per sec
>
> 2. What type and speed are the master and slave -> Master at 32 MHz,
> Slave at 150 MHz. SPI is configured at 1 MHz speed
> 3. If the clock rate is in the Mhz range, have you tried to slow it
> down?? [or put a delay between frames]-> 1 Bit delay per frame
> 4. Is the master missing entire frames?? or 'parts of frames'??
>
> This is the senario of my application:
>
> Master sends 17 Bytes /1.1ms interval where at the end there are some
> 150 us idle time.
>
> During 150 us Idle time, master produces an interrupt for a 4 byte
> long word data to be downloaded from slave to master. System can not
> afford to lose any word. Evey 1.1 ms time interval, Master must
> receive a valid word until all data is sent out. In this way Slave
> sends out 8 packet of data of 200 byte long each. So I have to send 50
> words in consecutive 50 1.1 ms intervals.
>
> I configured an interrupt routine to send out the word. Immediate
> after sending a word, i write 0 to DXR again. so that all byte out is
> 0 except the valid byte.
>
> Here are the problems what I am seeing:
>
> 1. If I send all 50 words are same value (any), it seems Master
> receive all and validate with checksum.
>
> I could not find an rational for what I am seeing:
>
> I have configured McBSP0 as a slave to talk to my external Master. I
> used 4 pins, CLK, SO, SI, and SS as frame sync for McBSP. I do not
> have any issue receving data from Master. However I am haveing some
> trouble in downloading data to Master. Seems losing data.
> >
> >I configure EDMA to trasfer data from McBSP receive register to a buffer in
memory. However I Did not configure any EDMA channel for Transmission event. In
order to transmit a word from McBSP I used polling method to watch XRDY pin of
SPCR and write the DXR register to shift the data out.
> >
> >My question is:
> >
> >Can anyone tell me if I have to configure any EDMA channel in order to use
the pulling method I am using.
> >
> >Any help will be appreciated.
> >
> >Thanks
> >
> >Sankar
> >
>
> >
> >
------- End of Original Message ------- Start a New Thread

Please ignore my last follow up posting: It was incomplete and i sent it accidentally:

I cut and past my lasting posing just for continution of my arguments:
Thanks a lot for your quick response. My SPI clock speed is 1 MHz. DSP is running at 150 MHz
and McBSP0 at 75 MHz.

1. What is the data rate -> 15KBytes per sec
2. What type and speed are the master and slave -> Master at 32 MHz, Slave at 150 MHz. SPI
is configured at 1 MHz speed
3. If the clock rate is in the Mhz range, have you tried to slow it
down?? [or put a delay between frames]-> 1 Bit delay per frame
4. Is the master missing entire frames?? or 'parts of frames'??

This is the senario of my application:

Master sends 17 Bytes /1.1ms interval where at the end there are some 150 us idle time.

During 150 us Idle time, master produces an interrupt for a 4 byte long word data to be
downloaded from slave to master. System can not afford to lose any word. Evey 1.1 ms time
interval, Master must receive a valid word until all data is sent out. In this way Slave sends
out 8 packet of data of 200 byte long each. So I have to send 50 words in consecutive 50 1.1 ms
intervals.

I configured an interrupt routine to send out the word. Immediate after sending a word, i write 0 to DXR again. so that all byte out is 0 except the valid byte.

In order to distinguish between valid and invalid byte we send a header for each word downloaded. We cannot download valid data every byte because of bandwidth issues dealt by Master and its buffer size.

Here are the problems what I am seeing:

1. If I send all 50 words are same value (any), it seems Master receive all and validate with
checksum.

I could not find an rational for what I am seeing:

1. If i send the same word (like say 0xFFAA5533) for all 50 words, Master receive them correctly and validates the checksum. However, if I send different data, checksum fails. That tells me that I am not probably writing DXR properly.

2. If i send consequetively only 20 words instead of 50, Master receives it correctly again. That confuses me.
I would like to try using CPU EVENT TRIGGER. Can anyone tell me if i configure EDMA for CPU event trigger using ESR register, How can i start over the EDMA event every time i trigger it.

Can anyone suggest me any better method to download data.

I have configured McBSP0 as a slave to talk to my external Master. I used 4 pins, CLK, SO, SI, and SS as frame sync for McBSP. I do not have any issue receving data from Master. However I am haveing some trouble in downloading data to Master. Seems losing data.
>
>I configure EDMA to trasfer data from McBSP receive register to a buffer in memory. However I Did not configure any EDMA channel for Transmission event. In order to transmit a word from McBSP I used polling method to watch XRDY pin of SPCR and write the DXR register to shift the data out.
>
>My question is:
>
>Can anyone tell me if I have to configure any EDMA channel in order to use the pulling method I am using.
>
>Any help will be appreciated.
>
>Thanks
>
>Sankar
> Start a New Thread

Hi friends,

I am using a TI 6713 processor. I want to know how the overflow and underflow are treated by TI 6713 processor, with respect to 32bit signed and float values.

To be more specific,

Num1,Num2 are 32bit signed float values
Num3,Num4 are 32bit unsigned integer values

Num1 = (3.4028E+38) + (3.4028E+38)
Num2 = (3.4028E+38) + (7.8E+2)

and

Num3 = (0xFFFFFFFF) + (0xFFFFFFFF)
Num4 = (0xFFFFFFFF) + (0xABCD1234)

Could anyone please tell me what are the values that goes into the
Num1, Num2, Num3 and Num4 ?

Thanks,
Yuvaraj Start a New Thread

On Wed, Nov 12, 2008 at 12:51 AM, yuvaraj wrote:
> Hi friends,
>
> I am using a TI 6713 processor. I want to know how the overflow and
> underflow are treated by TI 6713 processor, with respect to 32bit signed and
> float values.
>
> To be more specific,
>
> Num1,Num2 are 32bit signed float values
> Num3,Num4 are 32bit unsigned integer values
>
> Num1 = (3.4028E+38) + (3.4028E+38)
> Num2 = (3.4028E+38) + (7.8E+2)
>
> and
>
> Num3 = (0xFFFFFFFF) + (0xFFFFFFFF)
> Num4 = (0xFFFFFFFF) + (0xABCD1234)
>
> Could anyone please tell me what are the values that goes into the
> Num1, Num2, Num3 and Num4 ?


If you are writing assembly language programs, you will need to read
"TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide". The
FADCR, FAUCR, and FMCR register info is probably what you are looking
for [the behavior/mode of OF, UF, and RD can be controlled by the
programmer].

mikedunn
>
> Thanks,
> Yuvaraj

--
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