Virtex 5 EVM and DSK 6416 EMIF interface

Varun-

>> Second, are you asking Xilinx these questions? I don't see your posts on
>> comp.arch.fpga or Xilinx 'programmable
>> logic' forums. You are using an Xilinx app note as the key basis for your
>> design, so if you run into doubts then you
>> should ask Xilinx guys.
>> * I did search the Xilinx forums. Their latest document is unfortunately
> only for Virtex-4 interfacing with the DSK.*
>
> * WHen I called them up, they said only a professor could talk to Xilinx
> support (somepolicy). My prof is outta town,adding to more problems.*

You won't get far in your engineering career if you take no for an answer from vendors. Post your questions on the
groups I mentioned. You have to be persistent and determined.

-Jeff

>> > My guess is a hand-soldered 4" cable is going to be problematic for your
>> >> project -- 120 MHz clock and data transfers
>> >> are probably going to get smushed. You might look into Mictor type of
>> >> cables (individually shielded conductors);
>> >> these are used for logic analyzers. Another idea would be to use
>> >> LVDS-supported pins on the Virtex5 EVM board and
>> >> make (or purchase) a daughtercard for the DSK board that has LVDS
>> >> transceivers and an appropriate connector. I
>> >> suggest that you do some serious digging on this, and ask for advice
>> both
>> >> on Xilinx forum and TI e2e forum.
>> >>
>> >
>> > * I agree. Xilinx FPGA does have pins which support LVDS. I * checked
>> out
>> > *MICTOR ( ones mfg by signalogic too. ) I am very skeptical whether I
>> would
>> > be able to get* MICTORs that could mate with the Xilinx 0.05 inch
>> headers. I
>> > will have a look. Thanks a lot for your inputs Mr.Bower.
>> >
>> > Thanks,
>> >
>> >>
>> >> -Jeff
>> >>
>> >> >> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower <
>> j...@signalogic.com>
>> >> >> wrote:
>> >> >> >
>> >> >> >> Varoonian-
>> >> >> >>
>> >> >> >> > First of all, apologies for the really late reply as I fell
>> sick.
>> >> >> >> >
>> >> >> >> > I have posted my replies with *.*
>> >> >> >> >
>> >> >> >> > A couple of initial questions / comments:
>> >> >> >> >
>> >> >> >> > 1) How long do you plan to make the cable between DSK6416 and
>> >> Virtex-5
>> >> >> >> EVM?
>> >> >> >> > What type of cable are you using?
>> >> >> >> >
>> >> >> >> > *: Less than 4 inches. Since we are going to stack the DSP
>> and
>> >> FIFO
>> >> >> >> one
>> >> >> >> > above the other in order to reduce the cable length.*
>> >> >> >> >
>> >> >> >> > 2) Suggest to post to the group a two-column signal table, one
>> >> column
>> >> >> for
>> >> >> >> > EMIF and other for V5 EVM, like this:
>> >> >> >> >
>> >> >> >> > * Since some glue logic is required I have pasted the image
>> >> below
>> >> >> that
>> >> >> >> > describes the connectivity between the FPGA and the EMIF.*
>> >> >> >> >
>> >> >> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF
>> >> are
>> >> >> >> >
>> >> >> >> > [image: fifo2emif.bmp]
>> >> >> >> >
>> >> >> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in
>> >> the
>> >> >> >> SDRAM
>> >> >> >> > of the DSK 6416. This means that I need to perform a Peripheral
>> >> Device
>> >> >> >> > Transfer(PDT). Perform a PDT involves a different kind of
>> >> interfacing.
>> >> >> >> >
>> >> >> >> > [image: PDT.JPG]
>> >> >> >> >
>> >> >> >> > *When I looked up the DSK 6416 datasheet, I can't look up for
>> the
>> >> PDT
>> >> >> pin
>> >> >> >> on
>> >> >> >> > the EMIF A. Is the PDT pin an internal pin ??*
>> >> >> >>
>> >> >> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I
>> >> don't
>> >> >> >> know whether these pins are brought out to
>> >> >> >> the DSK daughtercard connector -- you have to study the DSK board
>> >> >> >> schematics. If not, then maybe you can find a PDT
>> >> >> >> test point on the DSK board and run a wire to an unused pin on the
>> >> >> >> daughtercard connector (or redefine an existing
>> >> >> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the
>> >> chip
>> >> >> :-(
>> >> >> >>
>> >> >> >> -Jeff
>> >> >> >>
>> >> >> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower <
>> >> j...@signalogic.com>
>> >> >> >> wrote:
>> >> >> >> >
>> >> >> >> >> Varun-
>> >> >> >> >>
>> >> >> >> >> > Does anyone know what is the interface used to connect the
>> >> Virtex-5
>> >> >> >> FPGA
>> >> >> >> >> and
>> >> >> >> >> > the the DSK6416 EMIF ?
>> >> >> >> >> >
>> >> >> >> >> > I know the connector to be used on the EMIF side is a Samtec
>> TMS
>> >> >> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with
>> the
>> >> >> >> >> Virtex-5.
>> >> >> >> >> >
>> >> >> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5
>> EVM
>> >> >> aren't
>> >> >> >> the
>> >> >> >> >> > same.
>> >> >> >> >>
>> >> >> >> >> A couple of initial questions / comments:
>> >> >> >> >>
>> >> >> >> >> 1) How long do you plan to make the cable between DSK6416 and
>> >> >> Virtex-5
>> >> >> >> EVM?
>> >> >> >> >> What type of cable are you using?
>> >> >> >> >>
>> >> >> >> >> 2) Suggest to post to the group a two-column signal table, one
>> >> column
>> >> >> >> for
>> >> >> >> >> EMIF and other for V5 EVM, like this:
>> >> >> >> >>
>> >> >> >> >> DSK6461 EMIF Virtex-5 EVM
>> >> >> >> >> ------------ ------------
>> >> >> >> >> AWE
>> >> >> >> >> CEn
>> >> >> >> >> ARDY
>> >> >> >> >> A2-Am Ai-Aj
>> >> >> >> >> D0-Dk D0-Dk
>> >> >> >> >>
>> >> >> >> >> where n, m, and i,j,k are to be determined, the objective being
>> to
>> >> >> >> define
>> >> >> >> >> signal equivalence and connectivity. There
>> >> >> >> >> is no point to worry about number of pins without first
>> carefully
>> >> >> >> >> considering the underlying design.
>> >> >> >> >>
>> >> >> >> >> -Jeff
>> >>
>> >>
>> >
>> >
>> > --
>> > Varun
>> >
> --
> Varun
>

_____________________________________ Start a New Thread

On Fri, Aug 20, 2010 at 12:40 AM, Jeff Brower wrote:

> Varun-
>
> >> Second, are you asking Xilinx these questions? I don't see your posts
> on
> >> comp.arch.fpga or Xilinx 'programmable
> >> logic' forums. You are using an Xilinx app note as the key basis for
> your
> >> design, so if you run into doubts then you
> >> should ask Xilinx guys.
> >>
> >
> > * I did search the Xilinx forums. Their latest document is
> unfortunately
> > only for Virtex-4 interfacing with the DSK.*
> >
> > * WHen I called them up, they said only a professor could talk to Xilinx
> > support (somepolicy). My prof is outta town,adding to more problems.*
>
> You won't get far in your engineering career if you take no for an answer
> from vendors. Post your questions on the
> groups I mentioned. You have to be persistent and determined.
>

* Yes!.. I will.*

>
> -Jeff
>
> >> > My guess is a hand-soldered 4" cable is going to be problematic for
> your
> >> >> project -- 120 MHz clock and data transfers
> >> >> are probably going to get smushed. You might look into Mictor type
> of
> >> >> cables (individually shielded conductors);
> >> >> these are used for logic analyzers. Another idea would be to use
> >> >> LVDS-supported pins on the Virtex5 EVM board and
> >> >> make (or purchase) a daughtercard for the DSK board that has LVDS
> >> >> transceivers and an appropriate connector. I
> >> >> suggest that you do some serious digging on this, and ask for advice
> >> both
> >> >> on Xilinx forum and TI e2e forum.
> >> >>
> >> >
> >> > * I agree. Xilinx FPGA does have pins which support LVDS. I *
> checked
> >> out
> >> > *MICTOR ( ones mfg by signalogic too. ) I am very skeptical whether I
> >> would
> >> > be able to get* MICTORs that could mate with the Xilinx 0.05 inch
> >> headers. I
> >> > will have a look. Thanks a lot for your inputs Mr.Bower.
> >> >
> >> > Thanks,
> >> >
> >> >>
> >> >> -Jeff
> >> >>
> >> >> >> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower <
> >> j...@signalogic.com>
> >> >> >> wrote:
> >> >> >> >
> >> >> >> >> Varoonian-
> >> >> >> >>
> >> >> >> >> > First of all, apologies for the really late reply as I fell
> >> sick.
> >> >> >> >> >
> >> >> >> >> > I have posted my replies with *.*
> >> >> >> >> >
> >> >> >> >> > A couple of initial questions / comments:
> >> >> >> >> >
> >> >> >> >> > 1) How long do you plan to make the cable between DSK6416 and
> >> >> Virtex-5
> >> >> >> >> EVM?
> >> >> >> >> > What type of cable are you using?
> >> >> >> >> >
> >> >> >> >> > *: Less than 4 inches. Since we are going to stack the DSP
> >> and
> >> >> FIFO
> >> >> >> >> one
> >> >> >> >> > above the other in order to reduce the cable length.*
> >> >> >> >> >
> >> >> >> >> > 2) Suggest to post to the group a two-column signal table,
> one
> >> >> column
> >> >> >> for
> >> >> >> >> > EMIF and other for V5 EVM, like this:
> >> >> >> >> >
> >> >> >> >> > * Since some glue logic is required I have pasted the
> image
> >> >> below
> >> >> >> that
> >> >> >> >> > describes the connectivity between the FPGA and the EMIF.*
> >> >> >> >> >
> >> >> >> >> > As per XAPP753 , the connections between the FIFO(FPGA) and
> EMIF
> >> >> are
> >> >> >> >> >
> >> >> >> >> > [image: fifo2emif.bmp]
> >> >> >> >> >
> >> >> >> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it
> in
> >> >> the
> >> >> >> >> SDRAM
> >> >> >> >> > of the DSK 6416. This means that I need to perform a
> Peripheral
> >> >> Device
> >> >> >> >> > Transfer(PDT). Perform a PDT involves a different kind of
> >> >> interfacing.
> >> >> >> >> >
> >> >> >> >> > [image: PDT.JPG]
> >> >> >> >> >
> >> >> >> >> > *When I looked up the DSK 6416 datasheet, I can't look up for
> >> the
> >> >> PDT
> >> >> >> pin
> >> >> >> >> on
> >> >> >> >> > the EMIF A. Is the PDT pin an internal pin ??*
> >> >> >> >>
> >> >> >> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet).
> I
> >> >> don't
> >> >> >> >> know whether these pins are brought out to
> >> >> >> >> the DSK daughtercard connector -- you have to study the DSK
> board
> >> >> >> >> schematics. If not, then maybe you can find a PDT
> >> >> >> >> test point on the DSK board and run a wire to an unused pin on
> the
> >> >> >> >> daughtercard connector (or redefine an existing
> >> >> >> >> pin). Hopefully the PDT pin is not "NC" and thus buried under
> the
> >> >> chip
> >> >> >> :-(
> >> >> >> >>
> >> >> >> >> -Jeff
> >> >> >> >>
> >> >> >> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower <
> >> >> j...@signalogic.com>
> >> >> >> >> wrote:
> >> >> >> >> >
> >> >> >> >> >> Varun-
> >> >> >> >> >>
> >> >> >> >> >> > Does anyone know what is the interface used to connect the
> >> >> Virtex-5
> >> >> >> >> FPGA
> >> >> >> >> >> and
> >> >> >> >> >> > the the DSK6416 EMIF ?
> >> >> >> >> >> >
> >> >> >> >> >> > I know the connector to be used on the EMIF side is a
> Samtec
> >> TMS
> >> >> >> >> >> > 140-32-S-D-LC but I have no idea about interfacing that
> with
> >> the
> >> >> >> >> >> Virtex-5.
> >> >> >> >> >> >
> >> >> >> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5
> >> EVM
> >> >> >> aren't
> >> >> >> >> the
> >> >> >> >> >> > same.
> >> >> >> >> >>
> >> >> >> >> >> A couple of initial questions / comments:
> >> >> >> >> >>
> >> >> >> >> >> 1) How long do you plan to make the cable between DSK6416
> and
> >> >> >> Virtex-5
> >> >> >> >> EVM?
> >> >> >> >> >> What type of cable are you using?
> >> >> >> >> >>
> >> >> >> >> >> 2) Suggest to post to the group a two-column signal table,
> one
> >> >> column
> >> >> >> >> for
> >> >> >> >> >> EMIF and other for V5 EVM, like this:
> >> >> >> >> >>
> >> >> >> >> >> DSK6461 EMIF Virtex-5 EVM
> >> >> >> >> >> ------------ ------------
> >> >> >> >> >> AWE
> >> >> >> >> >> CEn
> >> >> >> >> >> ARDY
> >> >> >> >> >> A2-Am Ai-Aj
> >> >> >> >> >> D0-Dk D0-Dk
> >> >> >> >> >>
> >> >> >> >> >> where n, m, and i,j,k are to be determined, the objective
> being
> >> to
> >> >> >> >> define
> >> >> >> >> >> signal equivalence and connectivity. There
> >> >> >> >> >> is no point to worry about number of pins without first
> >> carefully
> >> >> >> >> >> considering the underlying design.
> >> >> >> >> >>
> >> >> >> >> >> -Jeff
> >> >>
> >> >>
> >> >
> >> >
> >> > --
> >> > Varun
> >> >
> >>
> >>
> >
> >
> > --
> > Varun
> >
--
Varun Start a New Thread

On Fri, Aug 20, 2010 at 12:10 AM, Jeff Brower wrote:

> Varun-
>
> >> For a continuous stream of incoming data the typical method is double
> >> buffering (in your case, maybe split the FIFO in
> >> half, or have 2 FIFOs). When each buffer is full the DSP is notified
> and
> >> starts a DMA transfer, while input streaming
> >> continues in the other buffer. The buffer transfers toggle back and
> forth.
> >> To implement this, your FPGA would issue
> >> some type of "buffer full" interrupt. If Xilinx hasn't defined a signal
> >> for this then hopefully there is an unused
> >> pin you can use.
> >>
> > * So two FIFO's connected back to back. The one near the DSP bursts
> out
> > data when it is FULL.* Is that correct ?
>
> No, side-by-side. Your FPGA logic writes A/D samples into FIFO A. When
> FIFO A is full, your logic:
>
> -notifies the DSP
>
> -switches to FIFO B and continues
> writing A/D samples
>
> The DSP then performs DMA transfers from FIFO A to SDRAM. Your logic would
> mux the DSP EMIF control signals so they
> can be connected to either FIFO, as needed.
>
> Also it's worth pointing out that you could use dual-port RAM in the FPGA
> also. A double-buffer scheme doesn't really
> require FIFOs, plus the DSP can DMA transfer a buffer to SDRAM faster than
> your A/D 32-bit wide samples can fill one
> (at least we assume that, otherwise your project can never work).
* I have started designing the FIFO. Yes reading data from the FIFO must
be faster than the ADC writing data into it.*

*Thanks for the parallel FIFO idea. I will try to implement it.*

> > *The FIFO does have a FIFO full
> > signal and empty signal. Can you suggest any literature on this ?
>
> First I would think it's straightforward to connect various FIFO signals to
> pins that go to the expansion connector on
> the Virtex5 EVM. Have you tried this yet?
>

* Yes! I designed the FIFO using Core Generator and connected their pins
to the FPGA pins which are hardwired to the expansion connectors.*

>
> Second, are you asking Xilinx these questions? I don't see your posts on
> comp.arch.fpga or Xilinx 'programmable
> logic' forums. You are using an Xilinx app note as the key basis for your
> design, so if you run into doubts then you
> should ask Xilinx guys.
>

* I did search the Xilinx forums. Their latest document is unfortunately
only for Virtex-4 interfacing with the DSK.*

* WHen I called them up, they said only a professor could talk to Xilinx
support (somepolicy). My prof is outta town,adding to more problems.*

>
> -Jeff
>
> > My guess is a hand-soldered 4" cable is going to be problematic for your
> >> project -- 120 MHz clock and data transfers
> >> are probably going to get smushed. You might look into Mictor type of
> >> cables (individually shielded conductors);
> >> these are used for logic analyzers. Another idea would be to use
> >> LVDS-supported pins on the Virtex5 EVM board and
> >> make (or purchase) a daughtercard for the DSK board that has LVDS
> >> transceivers and an appropriate connector. I
> >> suggest that you do some serious digging on this, and ask for advice
> both
> >> on Xilinx forum and TI e2e forum.
> >>
> >
> > * I agree. Xilinx FPGA does have pins which support LVDS. I * checked
> out
> > *MICTOR ( ones mfg by signalogic too. ) I am very skeptical whether I
> would
> > be able to get* MICTORs that could mate with the Xilinx 0.05 inch
> headers. I
> > will have a look. Thanks a lot for your inputs Mr.Bower.
> >
> > Thanks,
> >
> >>
> >> -Jeff
> >>
> >> >> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower <
> j...@signalogic.com>
> >> >> wrote:
> >> >> >
> >> >> >> Varoonian-
> >> >> >>
> >> >> >> > First of all, apologies for the really late reply as I fell
> sick.
> >> >> >> >
> >> >> >> > I have posted my replies with *.*
> >> >> >> >
> >> >> >> > A couple of initial questions / comments:
> >> >> >> >
> >> >> >> > 1) How long do you plan to make the cable between DSK6416 and
> >> Virtex-5
> >> >> >> EVM?
> >> >> >> > What type of cable are you using?
> >> >> >> >
> >> >> >> > *: Less than 4 inches. Since we are going to stack the DSP
> and
> >> FIFO
> >> >> >> one
> >> >> >> > above the other in order to reduce the cable length.*
> >> >> >> >
> >> >> >> > 2) Suggest to post to the group a two-column signal table, one
> >> column
> >> >> for
> >> >> >> > EMIF and other for V5 EVM, like this:
> >> >> >> >
> >> >> >> > * Since some glue logic is required I have pasted the image
> >> below
> >> >> that
> >> >> >> > describes the connectivity between the FPGA and the EMIF.*
> >> >> >> >
> >> >> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF
> >> are
> >> >> >> >
> >> >> >> > [image: fifo2emif.bmp]
> >> >> >> >
> >> >> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in
> >> the
> >> >> >> SDRAM
> >> >> >> > of the DSK 6416. This means that I need to perform a Peripheral
> >> Device
> >> >> >> > Transfer(PDT). Perform a PDT involves a different kind of
> >> interfacing.
> >> >> >> >
> >> >> >> > [image: PDT.JPG]
> >> >> >> >
> >> >> >> > *When I looked up the DSK 6416 datasheet, I can't look up for
> the
> >> PDT
> >> >> pin
> >> >> >> on
> >> >> >> > the EMIF A. Is the PDT pin an internal pin ??*
> >> >> >>
> >> >> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I
> >> don't
> >> >> >> know whether these pins are brought out to
> >> >> >> the DSK daughtercard connector -- you have to study the DSK board
> >> >> >> schematics. If not, then maybe you can find a PDT
> >> >> >> test point on the DSK board and run a wire to an unused pin on the
> >> >> >> daughtercard connector (or redefine an existing
> >> >> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the
> >> chip
> >> >> :-(
> >> >> >>
> >> >> >> -Jeff
> >> >> >>
> >> >> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower <
> >> j...@signalogic.com>
> >> >> >> wrote:
> >> >> >> >
> >> >> >> >> Varun-
> >> >> >> >>
> >> >> >> >> > Does anyone know what is the interface used to connect the
> >> Virtex-5
> >> >> >> FPGA
> >> >> >> >> and
> >> >> >> >> > the the DSK6416 EMIF ?
> >> >> >> >> >
> >> >> >> >> > I know the connector to be used on the EMIF side is a Samtec
> TMS
> >> >> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with
> the
> >> >> >> >> Virtex-5.
> >> >> >> >> >
> >> >> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5
> EVM
> >> >> aren't
> >> >> >> the
> >> >> >> >> > same.
> >> >> >> >>
> >> >> >> >> A couple of initial questions / comments:
> >> >> >> >>
> >> >> >> >> 1) How long do you plan to make the cable between DSK6416 and
> >> >> Virtex-5
> >> >> >> EVM?
> >> >> >> >> What type of cable are you using?
> >> >> >> >>
> >> >> >> >> 2) Suggest to post to the group a two-column signal table, one
> >> column
> >> >> >> for
> >> >> >> >> EMIF and other for V5 EVM, like this:
> >> >> >> >>
> >> >> >> >> DSK6461 EMIF Virtex-5 EVM
> >> >> >> >> ------------ ------------
> >> >> >> >> AWE
> >> >> >> >> CEn
> >> >> >> >> ARDY
> >> >> >> >> A2-Am Ai-Aj
> >> >> >> >> D0-Dk D0-Dk
> >> >> >> >>
> >> >> >> >> where n, m, and i,j,k are to be determined, the objective being
> to
> >> >> >> define
> >> >> >> >> signal equivalence and connectivity. There
> >> >> >> >> is no point to worry about number of pins without first
> carefully
> >> >> >> >> considering the underlying design.
> >> >> >> >>
> >> >> >> >> -Jeff
> >>
> >>
> >
> >
> > --
> > Varun
> >
--
Varun Start a New Thread