Hello,
I'm trying to download the DSP Firmware code via PCI, that is I'm
working on PCI boot code. I use TI tool to convert the a.out file to C header
file and then I write the code from Linux x86 PC using device-driver to TI
DSP.
The fw code is just a simple switch statement, which will update the memory
location 0x3f000 from 0xa to 0x0 and HOST PC driver will write/read the content
of 0x3f000.
The C header file looks like as below:
const char BootTable[]={
/*Program Entry point*/
0x40, 0x0a, 0x00, 0x00,
/*Section .cinit begin*/
0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
0x60, 0x0b, 0x00, 0x00, /*Load address*/
0x60, 0x0b, 0x00, 0x00, /*Run address*/
/*Raw section Data*/
0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
/*Section .text begin*/
0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
0x00, 0x00, 0x00, 0x00, /*Load address*/
0x00, 0x00, 0x00, 0x00, /*Run address*/
/*Raw section Data*/
0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a,
0x00, 0x00, 0x02,
0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
Before downloading, I connect CCS and I make all the DSP RAM contents 0x00.
After I downloading the image from PCI host, I see the following at the 0 RAM
memory location:
0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata,
__edata, CSL_init, bss
0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x00000018 C$RL0
0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x0000002C C$RL1
0x0000002C 0x00000000 0x00000000 0x00000000
0x00000038 main
0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
0x0000006C C$RL2
0x0000006C 0x00000000 0x00000000
0x00000074 C$RL3
0x00000074 0x00000000 0x00000000
0x0000007C C$RL4
0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
But I see the correct raw content for .cinit code in the RAM.
So my question is:
1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of
all 0000s.
2. at 0xb60, I see the correct .cinit raw data.
Why I'm not able to see the correct raw data at 0x0 location for .text
section. Am I missing any steps. Does Linker stack, memory variable plays any
important role in this?
BTW, I'm not using a gel file, since my FW is very simple.
Thanks,
-yatin
_____________________________________
DSP memory content doesn't match with the binary image
Started by ●October 17, 2011
Reply by ●October 24, 20112011-10-24
Yatin-
In the first 24 locations of mem:
0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
something is basically wrong. .text, .bss, and other sections can't all start at the same place ("on top of each
other"). Such code would never run.
What's that area supposed to look like? I.e. after downloading via JTAG emulator?
-Jeff
> I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert
> the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>
> The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST
> PC driver will write/read the content of 0x3f000.
>
> The C header file looks like as below:
>
> const char BootTable[]={
> /*Program Entry point*/
> 0x40, 0x0a, 0x00, 0x00,
> /*Section .cinit begin*/
> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>
> /*Section .text begin*/
> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
> 0x00, 0x00, 0x00, 0x00, /*Load address*/
> 0x00, 0x00, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>
> Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI
> host, I see the following at the 0 RAM memory location:
>
> 0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
> 0x00000018 C$RL0
> 0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
> 0x0000002C C$RL1
> 0x0000002C 0x00000000 0x00000000 0x00000000
> 0x00000038 main
> 0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
> 0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
> 0x0000006C C$RL2
> 0x0000006C 0x00000000 0x00000000
> 0x00000074 C$RL3
> 0x00000074 0x00000000 0x00000000
> 0x0000007C C$RL4
> 0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>
> But I see the correct raw content for .cinit code in the RAM.
>
> So my question is:
>
> 1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>
> 2. at 0xb60, I see the correct .cinit raw data.
>
> Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker
> stack, memory variable plays any important role in this?
>
> BTW, I'm not using a gel file, since my FW is very simple.
>
> Thanks,
> -yatin
>
>
>
> _____________________________________
>
_____________________________________
In the first 24 locations of mem:
0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
something is basically wrong. .text, .bss, and other sections can't all start at the same place ("on top of each
other"). Such code would never run.
What's that area supposed to look like? I.e. after downloading via JTAG emulator?
-Jeff
> I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert
> the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>
> The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST
> PC driver will write/read the content of 0x3f000.
>
> The C header file looks like as below:
>
> const char BootTable[]={
> /*Program Entry point*/
> 0x40, 0x0a, 0x00, 0x00,
> /*Section .cinit begin*/
> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>
> /*Section .text begin*/
> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
> 0x00, 0x00, 0x00, 0x00, /*Load address*/
> 0x00, 0x00, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>
> Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI
> host, I see the following at the 0 RAM memory location:
>
> 0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
> 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
> 0x00000018 C$RL0
> 0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
> 0x0000002C C$RL1
> 0x0000002C 0x00000000 0x00000000 0x00000000
> 0x00000038 main
> 0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
> 0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
> 0x0000006C C$RL2
> 0x0000006C 0x00000000 0x00000000
> 0x00000074 C$RL3
> 0x00000074 0x00000000 0x00000000
> 0x0000007C C$RL4
> 0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>
> But I see the correct raw content for .cinit code in the RAM.
>
> So my question is:
>
> 1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>
> 2. at 0xb60, I see the correct .cinit raw data.
>
> Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker
> stack, memory variable plays any important role in this?
>
> BTW, I'm not using a gel file, since my FW is very simple.
>
> Thanks,
> -yatin
>
>
>
> _____________________________________
>
_____________________________________
Reply by ●October 24, 20112011-10-24
Jeff,
Thanks I resolved this issue by adding simple delay in my host download code.
Downloading from JTAG worked fine. As you already know, from Jtag we download a.out file which has some extra contents added to it but the a.out code runs fine from the jtag and all the memory content match the a.out file.
In case of downloading from PCI host, I found that I need to add delay for writing byte-after-byte. Even though I've not yet investigated the reason for adding this delay but adding delay worked.
Maybe I need to ack/check or verify each and every byte after downloading to the memory. Honestly I don't know what check/balance one need to do while downloading from Host.
Thanks,
-Yatin
Hello,
>
>I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>
>The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST PC driver will write/read the content of 0x3f000.
>
>The C header file looks like as below:
>
>const char BootTable[]={
> /*Program Entry point*/
> 0x40, 0x0a, 0x00, 0x00,
> /*Section .cinit begin*/
> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>
> /*Section .text begin*/
> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
> 0x00, 0x00, 0x00, 0x00, /*Load address*/
> 0x00, 0x00, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI host, I see the following at the 0 RAM memory location:
>
>0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
>0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x00000018 C$RL0
>0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000002C C$RL1
>0x0000002C 0x00000000 0x00000000 0x00000000
>0x00000038 main
>0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000006C C$RL2
>0x0000006C 0x00000000 0x00000000
>0x00000074 C$RL3
>0x00000074 0x00000000 0x00000000
>0x0000007C C$RL4
>0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>
>But I see the correct raw content for .cinit code in the RAM.
>
>So my question is:
>
>1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>
>2. at 0xb60, I see the correct .cinit raw data.
>
>Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker stack, memory variable plays any important role in this?
>
>BTW, I'm not using a gel file, since my FW is very simple.
>
>Thanks,
>-yatin
>
>_____________________________________
_____________________________________
Thanks I resolved this issue by adding simple delay in my host download code.
Downloading from JTAG worked fine. As you already know, from Jtag we download a.out file which has some extra contents added to it but the a.out code runs fine from the jtag and all the memory content match the a.out file.
In case of downloading from PCI host, I found that I need to add delay for writing byte-after-byte. Even though I've not yet investigated the reason for adding this delay but adding delay worked.
Maybe I need to ack/check or verify each and every byte after downloading to the memory. Honestly I don't know what check/balance one need to do while downloading from Host.
Thanks,
-Yatin
Hello,
>
>I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>
>The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST PC driver will write/read the content of 0x3f000.
>
>The C header file looks like as below:
>
>const char BootTable[]={
> /*Program Entry point*/
> 0x40, 0x0a, 0x00, 0x00,
> /*Section .cinit begin*/
> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>
> /*Section .text begin*/
> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
> 0x00, 0x00, 0x00, 0x00, /*Load address*/
> 0x00, 0x00, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI host, I see the following at the 0 RAM memory location:
>
>0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
>0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x00000018 C$RL0
>0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000002C C$RL1
>0x0000002C 0x00000000 0x00000000 0x00000000
>0x00000038 main
>0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000006C C$RL2
>0x0000006C 0x00000000 0x00000000
>0x00000074 C$RL3
>0x00000074 0x00000000 0x00000000
>0x0000007C C$RL4
>0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>
>But I see the correct raw content for .cinit code in the RAM.
>
>So my question is:
>
>1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>
>2. at 0xb60, I see the correct .cinit raw data.
>
>Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker stack, memory variable plays any important role in this?
>
>BTW, I'm not using a gel file, since my FW is very simple.
>
>Thanks,
>-yatin
>
>_____________________________________
_____________________________________
Reply by ●October 24, 20112011-10-24
Yatin-
> Thanks I resolved this issue by adding simple delay in my host download code.
Hmm. That means there is some issue with your driver and/or firmware on the card that interfaces to the C64x PCI. As
I recall from your previous posts, this is a C6412 card?
-Jeff
> Downloading from JTAG worked fine. As you already know, from Jtag we download a.out file which has some extra contents
> added to it but the a.out code runs fine from the jtag and all the memory content match the a.out file.
>
> In case of downloading from PCI host, I found that I need to add delay for writing byte-after-byte. Even though I've
> not yet investigated the reason for adding this delay but adding delay worked.
>
> Maybe I need to ack/check or verify each and every byte after downloading to the memory. Honestly I don't know what
> check/balance one need to do while downloading from Host.
>
> Thanks,
> -Yatin
>
> Hello,
>>
>>I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert
>> the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>>
>>The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST
>> PC driver will write/read the content of 0x3f000.
>>
>>The C header file looks like as below:
>>
>>const char BootTable[]={
>> /*Program Entry point*/
>> 0x40, 0x0a, 0x00, 0x00,
>> /*Section .cinit begin*/
>> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
>> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
>> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
>> /*Raw section Data*/
>> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>>
>> /*Section .text begin*/
>> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
>> 0x00, 0x00, 0x00, 0x00, /*Load address*/
>> 0x00, 0x00, 0x00, 0x00, /*Run address*/
>> /*Raw section Data*/
>> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
>> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>>Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI
>> host, I see the following at the 0 RAM memory location:
>>
>>0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
>>0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>>0x00000018 C$RL0
>>0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>>0x0000002C C$RL1
>>0x0000002C 0x00000000 0x00000000 0x00000000
>>0x00000038 main
>>0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>>0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
>>0x0000006C C$RL2
>>0x0000006C 0x00000000 0x00000000
>>0x00000074 C$RL3
>>0x00000074 0x00000000 0x00000000
>>0x0000007C C$RL4
>>0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>>
>>But I see the correct raw content for .cinit code in the RAM.
>>
>>So my question is:
>>
>>1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>>
>>2. at 0xb60, I see the correct .cinit raw data.
>>
>>Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker
>> stack, memory variable plays any important role in this?
>>
>>BTW, I'm not using a gel file, since my FW is very simple.
>>
>>Thanks,
>>-yatin
_____________________________________
> Thanks I resolved this issue by adding simple delay in my host download code.
Hmm. That means there is some issue with your driver and/or firmware on the card that interfaces to the C64x PCI. As
I recall from your previous posts, this is a C6412 card?
-Jeff
> Downloading from JTAG worked fine. As you already know, from Jtag we download a.out file which has some extra contents
> added to it but the a.out code runs fine from the jtag and all the memory content match the a.out file.
>
> In case of downloading from PCI host, I found that I need to add delay for writing byte-after-byte. Even though I've
> not yet investigated the reason for adding this delay but adding delay worked.
>
> Maybe I need to ack/check or verify each and every byte after downloading to the memory. Honestly I don't know what
> check/balance one need to do while downloading from Host.
>
> Thanks,
> -Yatin
>
> Hello,
>>
>>I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert
>> the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>>
>>The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST
>> PC driver will write/read the content of 0x3f000.
>>
>>The C header file looks like as below:
>>
>>const char BootTable[]={
>> /*Program Entry point*/
>> 0x40, 0x0a, 0x00, 0x00,
>> /*Section .cinit begin*/
>> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
>> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
>> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
>> /*Raw section Data*/
>> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>>
>> /*Section .text begin*/
>> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
>> 0x00, 0x00, 0x00, 0x00, /*Load address*/
>> 0x00, 0x00, 0x00, 0x00, /*Run address*/
>> /*Raw section Data*/
>> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
>> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>>Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI
>> host, I see the following at the 0 RAM memory location:
>>
>>0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
>>0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>>0x00000018 C$RL0
>>0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>>0x0000002C C$RL1
>>0x0000002C 0x00000000 0x00000000 0x00000000
>>0x00000038 main
>>0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>>0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
>>0x0000006C C$RL2
>>0x0000006C 0x00000000 0x00000000
>>0x00000074 C$RL3
>>0x00000074 0x00000000 0x00000000
>>0x0000007C C$RL4
>>0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>>
>>But I see the correct raw content for .cinit code in the RAM.
>>
>>So my question is:
>>
>>1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>>
>>2. at 0xb60, I see the correct .cinit raw data.
>>
>>Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker
>> stack, memory variable plays any important role in this?
>>
>>BTW, I'm not using a gel file, since my FW is very simple.
>>
>>Thanks,
>>-yatin
_____________________________________
Reply by ●October 24, 20112011-10-24
Yes, I'm using 6412 DSP.
Hello,
>
>I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>
>The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST PC driver will write/read the content of 0x3f000.
>
>The C header file looks like as below:
>
>const char BootTable[]={
> /*Program Entry point*/
> 0x40, 0x0a, 0x00, 0x00,
> /*Section .cinit begin*/
> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>
> /*Section .text begin*/
> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
> 0x00, 0x00, 0x00, 0x00, /*Load address*/
> 0x00, 0x00, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI host, I see the following at the 0 RAM memory location:
>
>0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
>0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x00000018 C$RL0
>0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000002C C$RL1
>0x0000002C 0x00000000 0x00000000 0x00000000
>0x00000038 main
>0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000006C C$RL2
>0x0000006C 0x00000000 0x00000000
>0x00000074 C$RL3
>0x00000074 0x00000000 0x00000000
>0x0000007C C$RL4
>0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>
>But I see the correct raw content for .cinit code in the RAM.
>
>So my question is:
>
>1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>
>2. at 0xb60, I see the correct .cinit raw data.
>
>Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker stack, memory variable plays any important role in this?
>
>BTW, I'm not using a gel file, since my FW is very simple.
>
>Thanks,
>-yatin
>
>_____________________________________
_____________________________________
Hello,
>
>I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>
>The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST PC driver will write/read the content of 0x3f000.
>
>The C header file looks like as below:
>
>const char BootTable[]={
> /*Program Entry point*/
> 0x40, 0x0a, 0x00, 0x00,
> /*Section .cinit begin*/
> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>
> /*Section .text begin*/
> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
> 0x00, 0x00, 0x00, 0x00, /*Load address*/
> 0x00, 0x00, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI host, I see the following at the 0 RAM memory location:
>
>0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
>0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x00000018 C$RL0
>0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000002C C$RL1
>0x0000002C 0x00000000 0x00000000 0x00000000
>0x00000038 main
>0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000006C C$RL2
>0x0000006C 0x00000000 0x00000000
>0x00000074 C$RL3
>0x00000074 0x00000000 0x00000000
>0x0000007C C$RL4
>0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>
>But I see the correct raw content for .cinit code in the RAM.
>
>So my question is:
>
>1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>
>2. at 0xb60, I see the correct .cinit raw data.
>
>Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker stack, memory variable plays any important role in this?
>
>BTW, I'm not using a gel file, since my FW is very simple.
>
>Thanks,
>-yatin
>
>_____________________________________
_____________________________________
Reply by ●November 4, 20112011-11-04
I solved it, thanks.
-Y
Hello,
>
>I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>
>The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST PC driver will write/read the content of 0x3f000.
>
>The C header file looks like as below:
>
>const char BootTable[]={
> /*Program Entry point*/
> 0x40, 0x0a, 0x00, 0x00,
> /*Section .cinit begin*/
> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>
> /*Section .text begin*/
> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
> 0x00, 0x00, 0x00, 0x00, /*Load address*/
> 0x00, 0x00, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI host, I see the following at the 0 RAM memory location:
>
>0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
>0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x00000018 C$RL0
>0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000002C C$RL1
>0x0000002C 0x00000000 0x00000000 0x00000000
>0x00000038 main
>0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000006C C$RL2
>0x0000006C 0x00000000 0x00000000
>0x00000074 C$RL3
>0x00000074 0x00000000 0x00000000
>0x0000007C C$RL4
>0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>
>But I see the correct raw content for .cinit code in the RAM.
>
>So my question is:
>
>1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>
>2. at 0xb60, I see the correct .cinit raw data.
>
>Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker stack, memory variable plays any important role in this?
>
>BTW, I'm not using a gel file, since my FW is very simple.
>
>Thanks,
>-yatin
>
>_____________________________________
_____________________________________
-Y
Hello,
>
>I'm trying to download the DSP Firmware code via PCI, that is I'm working on PCI boot code. I use TI tool to convert the a.out file to C header file and then I write the code from Linux x86 PC using device-driver to TI DSP.
>
>The fw code is just a simple switch statement, which will update the memory location 0x3f000 from 0xa to 0x0 and HOST PC driver will write/read the content of 0x3f000.
>
>The C header file looks like as below:
>
>const char BootTable[]={
> /*Program Entry point*/
> 0x40, 0x0a, 0x00, 0x00,
> /*Section .cinit begin*/
> 0x24, 0x02, 0x00, 0x00, /*Size in bytes*/
> 0x60, 0x0b, 0x00, 0x00, /*Load address*/
> 0x60, 0x0b, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0x04, 0x00, 0x00, 0x00, 0x88, 0x0d,........
>
> /*Section .text begin*/
> 0x60, 0x0b, 0x00, 0x00, /*Size in bytes*/
> 0x00, 0x00, 0x00, 0x00, /*Load address*/
> 0x00, 0x00, 0x00, 0x00, /*Run address*/
> /*Raw section Data*/
> 0xf6, 0x54, 0xbc, 0x01, 0x00, 0x20, 0x00, 0x00, 0x2a, 0x80, 0x05, 0x02, 0x6a, 0x00, 0x00, 0x02,
> 0x62, 0x03, 0x10, 0x00, 0x62, 0x81,
>Before downloading, I connect CCS and I make all the DSP RAM contents 0x00. After I downloading the image from PCI host, I see the following at the 0 RAM memory location:
>
>0x00000000 .text, __text, .bss, __bss, end, __end, .data, __data, edata, __edata, CSL_init, bss
>0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x00000018 C$RL0
>0x00000018 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000002C C$RL1
>0x0000002C 0x00000000 0x00000000 0x00000000
>0x00000038 main
>0x00000038 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000005C 0x00000000 0x00000000 0x00000000 0x00000000
>0x0000006C C$RL2
>0x0000006C 0x00000000 0x00000000
>0x00000074 C$RL3
>0x00000074 0x00000000 0x00000000
>0x0000007C C$RL4
>0x0000007C 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
>
>But I see the correct raw content for .cinit code in the RAM.
>
>So my question is:
>
>1. at 0 location I should see .text raw data 0xf6, 0x54, 0xbc, 0x0 instead of all 0000s.
>
>2. at 0xb60, I see the correct .cinit raw data.
>
>Why I'm not able to see the correct raw data at 0x0 location for .text section. Am I missing any steps. Does Linker stack, memory variable plays any important role in this?
>
>BTW, I'm not using a gel file, since my FW is very simple.
>
>Thanks,
>-yatin
>
>_____________________________________
_____________________________________
