Forums

reset FIFO flags

Started by vesenisti March 27, 2003
Hi there.

We are attempting to create an application that uses the PCI interface
to continuously transfer data from the C6201 EVM to the host where it
is written to a file. On the C6201 EVM we use two buffers, while one
is being transferred to the host the other is being filled with data.
Reading from the first buffer works OK, but when we read form the
second buffer on the host we get some residuals form the first
buffer. We have found an ad-hoc solution to this which involves
reading 44 bytes from the PCI interface before the real data is read,
we would however like to be able to reset the PCI interface between
reads, as we understand it this could be achieved by setting the bits
of BAR0 + 0xCB bits 25 and 26 (the host byte address of the MCSR
S5933 PCI Bus Operation Register reset FIFO flags) to some value (see
pages 1-29 and 1-36 of spru305). Unfortunately we haven't found a
hint of what BAR0 might be, is there anyone that might care to
enlighten us?

Also if someone might know why these old values are received some
clarification on that issue would be greatly appreciated.




There are several Base Address Registers (BAR0, BAR1, ... ) that are
dynamically assigned at bootup by the PCI BIOS. These registers can be read
via a dll under windowsNT (see attached .zip file containing code developed
by David Welch). For more information, the following site may be of value:

http://members.hyperlink.net.au/~chart/pci.htm

Bill Zimmerman

> Subject: [c6x] reset FIFO flags > Hi there.
>
> We are attempting to create an application that uses the PCI
> interface to continuously transfer data from the C6201 EVM to
> the host where it
> is written to a file. On the C6201 EVM we use two buffers, while one
> is being transferred to the host the other is being filled with data.
> Reading from the first buffer works OK, but when we read form the
> second buffer on the host we get some residuals form the first
> buffer. We have found an ad-hoc solution to this which involves
> reading 44 bytes from the PCI interface before the real data is read,
> we would however like to be able to reset the PCI interface between
> reads, as we understand it this could be achieved by setting the bits
> of BAR0 + 0xCB bits 25 and 26 (the host byte address of the MCSR
> S5933 PCI Bus Operation Register reset FIFO flags) to some value (see
> pages 1-29 and 1-36 of spru305). Unfortunately we haven't found a
> hint of what BAR0 might be, is there anyone that might care to
> enlighten us?
>


Attachment (not stored)
PCIINFO.ZIP
Type: application/x-zip-compressed