Any help with the following problem will be greatly appreciated.
Our c6202 chip is Silicon revision 1.2.
We are trying to boot the DSP via the XBUS. We are using a Motorola 8260 CPU as
the host, and a 6202 DSP as the slave. Our XBUS interface is setup to run in
Asynchronous Host Port mode. We are using the local bus of the 8260 as the XBUS.
The DSP has a boot configuration word of 0x22223107, where the boot mode is
internal MAP1, host boot. The only active signals we are using between the 8260
and the 6202 are the XD[0..31],XCS, XCNTL,XWR and XWE[0..3]. The XHOLD,XHOLDA,
andXBLAST lines are all pulled low via 1k resistors. The remaining lines,
XCE[0..3],XWE/XWAIT,XRE,XOE,XAS, and XRDY lines are all pulled high via 10k pull
The problem we are having is that we can read and write the DSPs program RAM
(0x00000000 to 0x0003FFFF), without any problem, but a write to any c6202 Data
Ram (0x80000000 to 0x8001FFFF) location does not appear to store correctly, at
It is our understanding that the host CPU should be able to read/write both
program and data RAM of the DSP while the DSP is in host boot mode, as well as
during normal program execution. Is this not a correct assumption ? Are we
missing some register setup in the DSP before attempting to access data RAM?
[ We tried also incorporating XRDY, in the CS logic generated by the 8260 so
that CS was returned HIGH when XRDY went back to teh HIGH state. This latter
test shortened the CS low pulse on the write but never reulted in CS returning
HIGH (after one day) when on the subsequent DRAM read was performed. On the DRAM
read, XRDY never went LOW]